M29W400BB-70N1

Manufacturer Part NumberM29W400BB-70N1
ManufacturerSTMicroelectronics
M29W400BB-70N1 datasheet
 
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Page 6/25

Download datasheet (239Kb)Embed
PrevNext
M29W400BT, M29W400BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
Put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will output the
IH
value, see Figure 9, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Table 5. Bus Operations, BYTE = V
Operation
E
Bus Read
V
IL
V
Bus Write
IL
Output Disable
X
Standby
V
IH
Read Manufacturer
V
IL
Code
V
Read Device Code
IL
Note: X = V
or V
.
IL
IH
Table 6. Bus Operations, BYTE = V
Operation
E
V
Bus Read
IL
V
Bus Write
IL
Output Disable
X
V
Standby
IH
Read Manufacturer
V
IL
Code
V
Read Device Code
IL
Note: X = V
or V
.
IL
IH
6/25
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figures 10 and 11, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
, to Chip Enable
Standby. When Chip Enable is High, V
IL
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
IL
Address Inputs
G
W
DQ15A–1, A0-A17
V
V
Cell Address
IL
IH
V
V
Command Address
IH
IL
V
V
X
IH
IH
X
X
X
A0 = V
, A1 = V
IL
IL
V
V
IL
IH
Others V
or V
IL
IH
A0 = V
, A1 = V
IH
IL
V
V
IL
IH
Others V
or V
IL
IH
IH
Address Inputs
G
W
A0-A17
V
V
Cell Address
IL
IH
V
V
Command Address
IH
IL
V
V
X
IH
IH
X
X
X
A0 = V
, A1 = V
IL
IL
V
V
IL
IH
Others V
or V
IL
IH
A0 = V
, A1 = V
IH
IL
V
V
IL
IH
Others V
or V
IL
IH
, during the whole Bus
IH
.
IH
, Chip Enable should
CC2
± 0.2V. For the Standby current
CC
, for Program or Erase operations un-
CC3
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Hi-Z
Data Output
Hi-Z
Data Input
Hi-Z
Hi-Z
, A9 = V
,
ID
Hi-Z
, A9 = V
,
EEh (M29W400BT)
ID
Hi-Z
EFh (M29W400BB)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
Hi-Z
, A9 = V
,
ID
0020h
, A9 = V
,
00EEh (M29W400BT)
ID
00EFh (M29W400BB)
, the
IH
Hi-Z
Hi-Z
20h