74ALVC541D,112 NXP Semiconductors, 74ALVC541D,112 Datasheet

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74ALVC541D,112

Manufacturer Part Number
74ALVC541D,112
Description
IC BUFF/DVR TRI-ST 8BIT 20SOIC
Manufacturer
NXP Semiconductors
Series
74ALVCr
Datasheet

Specifications of 74ALVC541D,112

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ALVC541D
74ALVC541D
935269734112
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74ALVC541D
74ALVC541PW
74ALVC541BQ
Ordering information
Package
Temperature range
40 C to +85 C
40 C to +85 C
40 C to +85 C
The 74ALVC541 is an octal non-inverting buffer/line drivers with 3-state bus compatible
outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1.
A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.
74ALVC541
Octal buffer/line driver; 3-state
Rev. 02 — 5 November 2007
Wide supply voltage range from 1.65 V to 3.6 V
Complies with JEDEC standard:
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.5 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Name
SO20
TSSOP20
DHVQFN20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual-in-line compatible thermal enhanced
very thin quad flat package no leads; 20 terminals;
body 2.5
4.5
0.85 mm
Product data sheet
Version
SOT163-1
SOT360-1
SOT764-1

Related parts for 74ALVC541D,112

74ALVC541D,112 Summary of contents

Page 1

Octal buffer/line driver; 3-state Rev. 02 — 5 November 2007 1. General description The 74ALVC541 is an octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. ...

Page 2

... NXP Semiconductors 4. Functional diagram Fig 1. Logic symbol 74ALVC541_2 Product data sheet mna179 Fig 2. IEC logic symbol Rev. 02 — 5 November 2007 74ALVC541 Octal buffer/line driver; 3-state 1 & mna180 © NXP B.V. 2007. All rights reserved ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74ALVC541 OE0 GND Fig 3. Pin configuration SO20, TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin OE0 1 A[0: GND 10 Y[0:7] 18, 17, 16, 15, 14, 13, 12, 11 data output OE1 74ALVC541_2 Product data sheet OE1 001aah060 (1) The die substrate is attached to this pad using Fig 4. Pin confi ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Control OE0 OE1 [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I input leakage current I I power-off leakage current V OFF I supply current CC I additional supply current CC C input capacitance I [1] All typical values are measured at V 10. Dynamic characteristics Table 7 ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions C power per buffer dissipation outputs enabled capacitance outputs disabled [1] All typical values are measured the same as t and PLH PHL t is the same as t and t ...

Page 8

... NXP Semiconductors OEn input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Enable and disable times Table 8. Measurement points Supply voltage Input ...

Page 9

... NXP Semiconductors Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor L Fig 7. Load circuitry for switching times Table 9. Test data Supply voltage Input 2 ...

Page 10

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Document ID Release date 74ALVC541_2 20071105 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...

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