74ABT652AD,118 NXP Semiconductors, 74ABT652AD,118 Datasheet
74ABT652AD,118
Specifications of 74ABT652AD,118
74ABT652AD-T
935192690118
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74ABT652AD,118 Summary of contents
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Octal transceiver/register; non-inverting; 3-state Rev. 02 — 12 March 2010 1. General description The 74ABT652A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT652A transceiver/register consists of bus transceiver ...
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... NXP Semiconductors 4. Block diagram CPBA 22 SBA 2 SAB 1 CPAB Fig 1. Logic symbol 74ABT652A_2 Product data sheet Octal transceiver/register; non-inverting; 3-state OEAB 3 OEBA 21 001aae845 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 02 — 12 March 2010 74ABT652A 21 EN1[BA] 3 EN2[AB] ...
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REAL TIME BUS TRANSFER REAL TIME BUS TRANSFER BUS B TO BUS OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA Fig 3. Real time bus transfer and storage STORAGE ...
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... NXP Semiconductors 21 OEBA 3 OEAB 23 CPBA 22 SBA 1 CPAB 2 SAB Fig 4. Logic diagram 74ABT652A_2 Product data sheet Octal transceiver/register; non-inverting; 3-state channels DETAIL A 7 All information provided in this document is subject to legal disclaimers. Rev. 02 — 12 March 2010 74ABT652A 001aae848 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol CPAB SAB OEAB A0, A1, A2, A3, A4, A5, A6, A7 GND B0, B1, B2, B3, B4, B5, B6, B7 OEBA SBA CPBA V CC 74ABT652A_2 Product data sheet Octal transceiver/register; non-inverting; 3-state ...
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... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function table Inputs OEAB OEBA CPAB [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH clock transition. [2] The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always enabled, i ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O T junction temperature j T storage temperature ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output voltage power-up LOW-level OL(pu) output voltage I input leakage current I I power-off leakage current V OFF I power-up/power-down O(pu/pd) output current I OFF-state output current output leakage current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter Conditions f maximum see max frequency t LOW to HIGH CPAB CPBA to An; see PLH propagation delay An; see SAB SBA to An; see t HIGH to LOW CPAB CPBA to An; see ...
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... NXP Semiconductors 11. Waveforms max V I CPBA CPAB GND PHL 1 Fig 6. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency SBA or SAB Fig 8. Propagation delay, SBA SAB to Bn An, Bn CPBA or CPAB The shaded areas indicate when the input is permitted to change for predictable output performance. ...
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... NXP Semiconductors OEBA OEAB 1 Fig 10. 3-state output enable time to HIGH-level and output disable time from HIGH-level OEBA OEAB 1 Fig 11. 3-state output enable time to LOW-level and output disable time from LOW-level 74ABT652A_2 Product data sheet Octal transceiver/register; non-inverting; 3-state GND t PZH V OH ...
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... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data and V levels are given in EXT R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 12. Test circuit for measuring switching times Table 8 ...
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... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 14. Package outline SOT340-1 (SSOP24) ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Release date 74ABT652A_2 20100312 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP 24 (SOT222-1) package removed from “Package ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT652A_2 Product data sheet Octal transceiver/register; non-inverting; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 12 March 2010 74ABT652A © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefi Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline ...