74ABT657DB,118 NXP Semiconductors, 74ABT657DB,118 Datasheet

IC TRANSCVR TRI-ST 8BIT 24SSOP

74ABT657DB,118

Manufacturer Part Number
74ABT657DB,118
Description
IC TRANSCVR TRI-ST 8BIT 24SSOP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet

Specifications of 74ABT657DB,118

Logic Type
Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ABT657DB-T
74ABT657DB-T
935069180118
1. General description
2. Features and benefits
The 74ABT657 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input
(pin T/R) determines the direction of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)
enables data from B ports to A ports.
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even
parity output, depending on the system. Pin PARITY is an output from the
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input
when receiving from port B to port A port (pin T/R = LOW).
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port
A is even, pin PARITY output goes LOW, keeping even parity.
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port
B is:
I
I
I
I
I
I
74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 — 15 March 2010
Combinational functions in one package
Low static and dynamic power dissipation with high speed and high output drive
Output capability: +64 mA and 32 mA
Power-up 3-state
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error
Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
N
N
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Product data sheet

Related parts for 74ABT657DB,118

74ABT657DB,118 Summary of contents

Page 1

Octal transceiver with parity generator/checker; 3-state Rev. 03 — 15 March 2010 1. General description The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT657 is an octal ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ABT657D +85 C 74ABT657DB +85 C 74ABT657PW + Functional diagram Fig 1. Logic symbol Fig 2. IEC logic symbol 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state Description SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 SSOP24 plastic shrink small outline package ...

Page 3

... NXP Semiconductors 1 T ODD/EVEN Fig 3. Logic diagram 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 74ABT657 13 PARITY PARITY 12 ERROR 001aae828 © NXP B.V. 2010. All rights reserved. ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol T ODD/EVEN ERROR PARITY GND OE 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state 74ABT657 1 T ODD/EVEN 11 12 ERROR 001aae825 Pin 23, 22, 21, 20, 17, 16, 15, 14 ...

Page 5

... NXP Semiconductors 6. Functional description 6.1 Function selection [1] Table 3. Function selection Number of Inputs inputs HIGH and 8 L (even and 7 L (odd Don’t care H [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state ...

Page 6

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O T junction temperature j T storage temperature ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output voltage input leakage current I I power-off leakage OFF current I power-up/power-down O(pu/pd) output current I OFF-state output current output leakage current LO I output current O I supply current ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter Conditions t LOW to HIGH An; see PLH propagation delay An to PARITY; see ODD/EVEN to PARITY and ERROR; see Bn to ERROR; see PARITY to ERROR; see t HIGH to LOW An; see PHL propagation delay An to PARITY ...

Page 9

... NXP Semiconductors 11. Waveforms Fig 5. Fig 6. Fig 7. 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state V I An, Bn, ODD/EVEN PARITY GND V OH PARITY, ERROR 1 Propagation delay for inverting output V I An, Bn, ODD/EVEN V PARITY GND V OH An, Bn, PARITY, ERROR 1 Propagation delay for non-inverting output ...

Page 10

... NXP Semiconductors Fig negative V M pulse positive V M pulse Input pulse definition Test data and V levels are given in EXT R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 9. ...

Page 11

... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 11. Package outline SOT340-1 (SSOP24) ...

Page 13

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... Release date 74ABT657_3 20100315 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP 24 (SOT222-1) package removed from “Package ...

Page 15

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 16

... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT657_3 Product data sheet Octal transceiver with parity generator/checker; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 74ABT657 © ...

Page 17

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefi Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function selection Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline ...

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