IC TRANSCVR 8BIT N-INV 24SSOP

74ABT646ADB,112

Manufacturer Part Number74ABT646ADB,112
DescriptionIC TRANSCVR 8BIT N-INV 24SSOP
ManufacturerNXP Semiconductors
Series74ABT
74ABT646ADB,112 datasheet
 

Specifications of 74ABT646ADB,112

Logic TypeRegistered Transceiver, Non-InvertingPackage / Case24-SSOP
Number Of Elements1Number Of Bits Per Element8
Current - Output High, Low32mA, 64mAVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Logic FamilyABTNumber Of Channels Per Chip8
Input LevelTTLOutput LevelTTL
Output Type3-StateHigh Level Output Current- 32 mA
Low Level Output Current64 mAPropagation Delay Time5.2 ns
Supply Voltage (max)5.5 VSupply Voltage (min)4.5 V
Maximum Operating Temperature+ 85 CFunctionBus Transceiver / Register
Input Bias Current (max)30000 uAMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTPolarityNon-Inverting
Number Of Circuits1Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names74ABT646ADB
74ABT646ADB
935192640112
  
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74ABT646A
Octal bus transceiver/register; 3-state
Rev. 03 — 15 March 2010
1. General description
The 74ABT646A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A bus or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver
function. In the transceiver mode, data present at the high-impedance port may be stored
in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real-time. The DIR pin determines which bus receives data when OE is active
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register
and/or data from bus B may be stored in the A register. When an output function is
disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time. The examples in
“Real time bus transfer and storage” on page 6
management functions that can be performed with the 74ABT646A.
2. Features and benefits
I
Combines 74ABT245 and 74ABT373A type functions in one device
I
Independent registers for A and B buses
I
Multiplexed real-time and stored data
I
Live insertion and extraction permitted
I
Output capability: +64 mA to 32 mA
I
Power-up 3-state
I
Power-up reset
I
Latch-up protection exceeds 500 mA per JESD78B class II level A
I
ESD protection:
N
HBM JESD22-A114F exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Product data sheet
Figure 5
demonstrate the four fundamental bus

74ABT646ADB,112 Summary of contents

  • Page 1

    Octal bus transceiver/register; 3-state Rev. 03 — 15 March 2010 1. General description The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT646A transceiver/register consists of bus transceiver ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74ABT646AD +85 C 74ABT646ADB +85 C 74ABT646APW + Functional diagram CPAB 2 SAB 3 DIR 23 CPBA 22 SBA Fig 1. Logic symbol 74ABT646A_3 Product data sheet Name Description SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 SSOP24 plastic shrink small outline package ...

  • Page 3

    ... NXP Semiconductors DIR 23 CPBA 22 SBA 1 CPAB 2 SAB Fig 3. Logic diagram 74ABT646A_3 Product data sheet channels DETAIL A 7 All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 74ABT646A Octal bus transceiver/register; 3-state 001aae894 © NXP B.V. 2010. All rights reserved. ...

  • Page 4

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol CPAB SAB DIR A0, A1, A2, A3, A4, A5, A6, A7 GND B0, B1, B2, B3, B4, B5, B6 SBA CPBA V CC 74ABT646A_3 Product data sheet 74ABT646A CPAB SAB DIR GND 12 13 ...

  • Page 5

    ... NXP Semiconductors 6. Functional description [1] Table 3. Function table Inputs OE DIR CPAB [ HIGH voltage level LOW voltage level don’t care; = LOW-to-HIGH clock transition; [2] The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock. ...

  • Page 6

    REAL TIME BUS TRANSFER REAL TIME BUS TRANSFER BUS B TO BUS DIR CPAB CPBA SAB SBA OE DIR Fig 5. Real time bus transfer and storage STORAGE ...

  • Page 7

    ... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current O T junction temperature j T storage temperature ...

  • Page 8

    ... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output voltage power-up LOW-level OL(pu) output voltage I input leakage current I I power-off leakage current V OFF I power-up/power-down O(pu/pd) output current I OFF-state output current output leakage current ...

  • Page 9

    ... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter f maximum frequency see max t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay t OFF-state to HIGH PZH propagation delay t OFF-state to LOW PZL propagation delay t HIGH to OFF-state ...

  • Page 10

    ... NXP Semiconductors 11. Waveforms and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay clock input to output and clock pulse width, maximum clock frequency SBA or SAB 1 and V are typical voltage output levels that occur with the output load. ...

  • Page 11

    ... NXP Semiconductors OE, DIR 1 and V are typical voltage output levels that occur with the output load Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level An, Bn CPBA or CPAB and V are typical voltage output levels that occur with the output load. ...

  • Page 12

    ... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 11. Load circuitry for switching times Table 8 ...

  • Page 13

    ... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 14

    ... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 13. Package outline SOT340-1 (SSOP24) ...

  • Page 15

    ... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 16

    ... Release date 74ABT646A_3 20100315 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP 24 (SOT222-1) package removed from “Package ...

  • Page 17

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 18

    ... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT646A_3 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 March 2010 74ABT646A Octal bus transceiver/register; 3-state © NXP B.V. 2010. All rights reserved. ...

  • Page 19

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefi Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...