M25P128-VME6TP Numonyx, B.V., M25P128-VME6TP Datasheet
M25P128-VME6TP
Related parts for M25P128-VME6TP
M25P128-VME6TP Summary of contents
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... JEDEC standard two-byte signature (2018h) ■ More than 10000 Erase/Program cycles per sector ■ More than 20-year data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 with 50-MHz SPI bus interface = Rev 3 M25P128 VDFPN8 (ME) 8x6mm (MLP8) SO16 (MF) 300 mils width 1/45 www.numonyx.com 1 ...
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... Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12 4.4 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/45 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 M25P128 ) . . . . . . . . . . . . . 9 PP ...
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... M25P128 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Part numbering ...
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... Table 13. DC characteristics Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 42 Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4/45 M25P128 ...
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... M25P128 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 ...
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... Summary description 1 Summary description The M25P128 is a 128 Mbit (16 Mbit × 8), multilevel Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256 bytes wide ...
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... Figure 3. SO connections Don’t Use 2. See Package mechanical M25P128 HOLD W section for package dimensions, and how to identify pin-1. M25P128 HOLD section for package dimensions, and how to identify pin-1 ...
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... The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 8/45 M25P128 ...
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... M25P128 2.6 Write Protect/Enhanced Program supply voltage (W/V W/V is both a control input and a power supply pin. The two functions are selected by the PP voltage range applied to the pin. If the W/V input is kept in a low voltage range ( input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register) ...
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... High at the same time, and so, that the t 10/ SPI memory (2) (2) R device S W/V HOLD S PP requirement is met). SHCH Figure 5, is the clock polarity when the SPI memory SPI memory (2) R device device W/V HOLD S W M25P128 HOLD AI12836 ...
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... M25P128 Figure 5. SPI modes supported CPOL CPHA MSB Q SPI modes MSB AI01438B 11/45 ...
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... W/V 12/45 Table 14: AC characteristics applied to the W/V PPH must be within the normal operating range): CC pin must be equal must be 25°C ±10° Section 6.8: Page , pin. PP (see Table 10) PPH should be less than 80 hours PPH M25P128 ). The BE ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms: ● Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... Upper 8nd (8 Sectors, 16Mb) 1 Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47) 0 Upper Half (32 Sectors, 64Mb) 1 All sectors (64 Sectors, 128Mb) Figure 6). M25P128 Unprotected area (1) All Sectors (Sectors 0 to 63) Sectors Sectors Sectors Sectors Lower Half (Sectors 0 to 31) ...
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... M25P128 Figure 6. Hold condition activation C HOLD Hold Condition (standard use) Operating features Hold Condition (non-standard use) AI02029D 15/45 ...
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... Sector or Bulk Erasable (bits are erased from but not Page Erasable. Figure 7. Block diagram HOLD W/V Control Logic Address Register and Counter 16/45 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Bytes (Page Size) X Decoder M25P128 Status Register FFFFFFh Size of the read-only memory area 000FFh AI11316b ...
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... M25P128 Table 3. Memory organization Sector Address Range FC0000h F80000h F40000h F00000h EC0000h E80000h E40000h E00000h DC0000h D80000h D40000h D00000h CC0000h C80000h C40000h C00000h BC0000h ...
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... M25P128 73FFFFh 6FFFFFh 6BFFFFh 67FFFFh 63FFFFh 5FFFFFh 5BFFFFh 57FFFFh 53FFFFh 4FFFFFh 4BFFFFh 47FFFFh 43FFFFh 3FFFFFh 3BFFFFh 37FFFFh 33FFFFh 2FFFFFh 2BFFFFh 27FFFFh ...
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... M25P128 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 20/45 (Figure 8) sets the Write Enable Latch (WEL) bit Instruction D High Impedance Q (Figure 9) resets the Write Enable Latch (WEL) bit Instruction D High Impedance Q M25P128 AI02281E AI03750D ...
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... M25P128 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (18h) ...
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... Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become 22/ BP2 Figure 11. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit Table 2) becomes ) is driven Low M25P128 b0 WIP ...
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... M25P128 read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Instruction Status Register Out ...
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... BP2, BP1 and BP0 bits can be changed Status Register is Hardware write protected Hardware Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed sizes. M25P128 ) is W Memory Content (1) Protected Area Unprotected Area Protected against Ready to accept Page Program, Page Program and ...
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... M25P128 Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/V When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/V ● ...
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... Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence High Impedance Q 26/45 Figure 13 Instruction 24-Bit Address MSB Data Out MSB M25P128 Data Out 2 7 AI03748D ...
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... M25P128 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 28/45 Table 2 and Table 3) is not executed. M25P128 Table 14: AC ...
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... M25P128 Figure 15. Page Program (PP) instruction sequence MSB Instruction 24-Bit Address MSB Data Byte 2 Data Byte MSB ...
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... BP1, BP0) bits (see Figure 16. Sector Erase (SE) instruction sequence 30/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 16. Table 2 and Table 3) is not executed Instruction 23 22 MSB Bit Address M25P128 ) is AI03751D ...
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... M25P128 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... WI VSL – all operations are disabled, and WI threshold. However, the WI is still below V CC (min), the device can be CC delay is not yet fully elapsed. should attain V CC CCMIN M25P128 is less CC (min). CC supply. CC before V PPH ...
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... M25P128 Figure 18. Power-up timing (max (min) Reset State of the Device V WI Table 8. Power-Up Timing and V Symbol ( (min Low VSL CC (1) t Time delay to Write instruction PUW V Write Inhibit Voltage WI 1. These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh) ...
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... Input and output voltage (with respect to Ground Supply voltage CC V Fast Program/Erase voltage PP V Electrostatic Discharge Voltage (Human Body Model) ESD 1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 34/45 Table 9 may cause permanent damage to Parameter (1) M25P128 Min. Max. Unit –65 150 °C –0 0 –0.2 4.0 V –0.2 10.0 V – ...
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... M25P128 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... open PPH PPH I = 1.6mA OL = –100μA IOH M25P128 Min. Max. Unit ± 2 µA ± 2 µA 100 µ – 0.5 0. ...
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... M25P128 Table 14. AC characteristics Symbol Alt ( CLH ( CLL (2) t CLCH (2) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS t t CLQV CLQX ...
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... C tDVCH D Q 38/45 Test conditions specified in Table 10 Parameter Bulk Erase Cycle Time Bulk Erase Cycle Time ( PPH (max). C tSLCH tCHDX MSB IN High Impedance and Table 11 Min. Typ. Max. 105 250 ( tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C M25P128 Unit s ...
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... M25P128 Figure 21. Write Protect setup and hold timing during WRSR when SRWD =1 W/V PP tWHSL High Impedance Q Figure 22. Hold timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX DC and AC parameters tSHWL AI07439b tHHCH AI02032 39/45 ...
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... DC and AC parameters Figure 23. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 24. V timing PPH PPH W/V PP tVPPHSL 40/45 tCH tCLQV End of PP (identified by WPI polling) PP, SE, BE M25P128 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449e ai12092 ...
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... M25P128 11 Package mechanical Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm, ...
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... Typ Min Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 – – 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° 0. 45˚ C θ ddd inches Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 0.050 – 0.394 0.010 0.016 0° M25P128 Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 ...
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... Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M25P128 – Part numbering ...
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... Threshold. Modified information and Section 6.8: Page Program Table 17. Read Electronic Signature (RES) parameter updated in Table 13: DC CC1 Write Protect/Enhanced Program ). Section 4.4: Fast Program/Erase mode added. Power-up specified for Fast Power-up and power-down section. ratings. M25P128 (RDID). value in VSL and modified data. ...
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... M25P128 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...