M25PE16-VMW6TP Numonyx, B.V., M25PE16-VMW6TP Datasheet
M25PE16-VMW6TP
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M25PE16-VMW6TP Summary of contents
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... Hardware write protection of the memory area selected using the BP0, BP1 and BP2 bits More than 100 000 write cycles More than 20 years data retention Packages – ECOPACK® (RoHS compliant) April 2008 VFQFPN8 (MP (MLP8) SO8W (MW) 208 mils width Rev 6 M25PE16 1/58 www.numonyx.com 1 ...
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... Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active power, standby power and deep power-down modes . . . . . . . . . . 13 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 4.8.2 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Write enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 2/58 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15 M25PE16 ...
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... M25PE16 6.4 Read status register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write status register (WRSR 6.6 Read data bytes (READ 6.7 Read data bytes at higher speed (FAST_READ 6.8 Read lock register (RDLR 6.9 Page write (PW 6.10 Page program (PP 6.11 Write to lock register (WRLR 6.12 Page erase (PE 6.13 Sector erase (SE 6.14 Subsector erase (SSE ...
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... Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 22. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23. SO8 wide – 8 lead plastic small outline, 208 mils body width, mechanical data Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4/58 M25PE16 ...
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... M25PE16 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 24 Figure 9 ...
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... Description 1 Description The M25PE16 is a 16-Mbit (2 Mbits × 8) serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle ...
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... M25PE16 W Reset V SS Function Serial clock Serial data input Serial data output Chip select Write protect Reset Supply voltage Ground M25PE16 for package dimensions, and how to identify pin-1. Q AI12343c Direction Input Input Output Input Input Input – ...
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... Reset Low pulse. 2.6 Write protect (W) The write protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the status register). See 8/58 Section 6.4: Read status register M25PE16 (RDSR). ...
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... M25PE16 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal descriptions 9/58 ...
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... Resistors R (represented in that the M25PE16 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
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... M25PE16 Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the bus p MSB ...
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... For optimized timings recommended to use the page write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (PW) sequences with each containing only a few bytes (see Table 18: AC characteristics (50 MHz operation)). 12/58 Section 6.9: Page write operation), and Table 19: AC characteristics (75 MHz M25PE16 (PW), ...
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... M25PE16 4.3 A fast way to modify data The page program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had previously been set to ‘1’. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (PE), subsector erase (SSE), sector erase (SE) or bulk erase (BE) instruction ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this and to meet the needs of modularized applications, the M25PE16 features the following flexible data protection mechanisms: 4.8.1 Protocol-related protections Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
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... M25PE16 4.8.2 Specific hardware and software protections There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be hardware protected with the help of the W input pin. SPM1 and SPM2 The first software protected mode (SPM1) is managed by specific lock registers assigned to each 64 Kbyte sector ...
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... Upper eighth (four sectors 31) Upper quarter (eight sectors 31) Upper half (sixteen sectors 31) Lower half (16 sectors 15) All sectors (32 sectors 31) All sectors (32 sectors 31) M25PE16 Unprotected area (1) All sectors (32 sectors 31) Lower 31st/32nd (31 sectors 30) Lower 15/16ths (30 sectors 29) ...
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... M25PE16 5 Memory organization The memory is organized as: 8192 pages (256 bytes each). 2,097,152 bytes (8 bits each) 32 sectors (512 Kbits, 65536 bytes each) 512 subsectors (32 Kbits, 4096 bytes each) Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is page, sector or bulk erasable (bits are erased from ...
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... C0000h C0FFFh BF000h BFFFFh 2 B0000h B0FFFh AF000h AFFFFh 1 A0000h A0FFFh 9F000h 9FFFFh 90000h 90FFFh 8F000h 8FFFFh 0 80000h 80FFFh 7F000h 7FFFFh 70000h 70FFFh M25PE16 Address range 111 6F000h 6FFFFh 96 60000h 60FFFh 95 5F000h 5FFFFh 80 50000h 50FFFh 79 4F000h 4FFFFh 64 40000h 40FFFh 63 3F000h 3FFFFh 48 30000h ...
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... M25PE16 Figure 5. Block diagram Reset W Control logic Address register and counter High voltage generator I/O shift register 256-byte data buffer 1FFFFFh Whole memory array can be made read-only on a 64-Kbyte basis through the lock registers 00000h 000FFh 256 bytes (page size) ...
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... Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write cycle, program cycle or erase cycle are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected. 20/58 Table 5. M25PE16 ...
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... M25PE16 Table 5. Instruction set Instruction WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRSR Write status register WRLR Write to lock register RDLR Read lock register READ Read data bytes Read data bytes at higher FAST_READ speed PW Page write ...
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... The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 6. Write enable (WREN) instruction sequence 22/58 (Figure 6) sets the write enable latch (WEL) bit Instruction D High Impedance Q M25PE16 AI02281E ...
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... M25PE16 6.2 Write disable (WRDI) The write disable (WRDI) instruction The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions: Power-up ...
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... Table 6. Read identification (RDID) data-out sequence Manufacturer identification Memory type 20h Figure 8. Read identification (RDID) instruction sequence and data-out sequence 24/58 Figure 8. Device identification Memory capacity 80h 15h M25PE16 UID CFD length CFD content 10h 16 bytes ...
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... M25PE16 6.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write cycle is in progress. When one of these cycles is in progress recommended to check the write in progress (WIP) bit before sending a new instruction to the device ...
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... Figure 9. Read status register (RDSR) instruction sequence and data-out sequence High Impedance Q 26/ Instruction Status register out MSB Status register out MSB M25PE16 0 7 AI02031E ...
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... M25PE16 6.5 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded and executed, the device sets the write enable latch (WEL) ...
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... BP2, BP1 and BP0 bits can be changed Status register is hardware write protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed M25PE16 Memory content (1) Protected area Unprotected area Protected against Ready to accept page program, page program and ...
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... M25PE16 6.6 Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... Instruction 24-bit address High Impedance Dummy byte DATA OUT MSB DATA OUT MSB M25PE16 0 7 MSB AI04006 ...
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... M25PE16 6.8 Read lock register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the read lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of Serial Clock (C) ...
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... Chip Select RHSL (S) Low. For the value and AC parameters. 32/58 Figure 14. pulse). On Reset going Low, the device enters the reset mode and see Table 21: Timings after a Reset Low pulse RHSL M25PE16 Table 12: Device in Section 11: ...
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... M25PE16 Figure 14. Page write (PW) instruction sequence Data byte MSB 1. Address bits A23 to A21 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB ...
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... Section 11: DC and AC 34/58 Figure 15. and Table 19: AC characteristics (75 MHz pulse). On Reset going Low, the device enters the reset is then required before the device can be re-selected by driving RHSL see Table 21: Timings after a Reset Low pulse RHSL parameters. M25PE16 Table 18: AC operation)). Table 12: in ...
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... M25PE16 Figure 15. Page program (PP) instruction sequence Data byte MSB 1. Address bits A23 to A21 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB ...
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... Instruction 24-bit address MSB Bit b7-b2 b1 Sector lock down bit value (refer to b0 Sector write lock bit value (refer to minimum value Lock register MSB Value ‘0’ Table 9) Table 9) M25PE16 AI10784 ...
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... M25PE16 6.12 Page erase (PE) The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Chip Select (S) Figure 18. see Table 21: Timings after a Reset Low pulse Instruction 23 22 MSB Table 12: Device status after a in Section 11: DC and 24-bit address M25PE16 ) is SE AI03751D ...
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... M25PE16 6.14 Subsector erase (SSE) The subsector erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Chip Select (S) Low. RHSL For the value of t RHSL AC parameters. Figure 20. Bulk erase (BE) instruction sequence 40/58 Figure 20. see Table 21: Timings after a Reset Low pulse Instruction initiated. While the BE Table 12: Device status after in Section 11: DC and AI03752D M25PE16 ...
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... M25PE16 6.16 Deep power-down (DP) Executing the deep power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. ...
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... Figure 22. Release from deep power-down (RDP) instruction sequence 42/58 Figure 22 Instruction High Impedance Deep power-down mode M25PE16 , the device is put in the RDP t RDP Standby mode AI06807 ...
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... M25PE16 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included ...
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... These parameters are characterized only, over the temperature range –40 °C to +85 °C. 44/58 Program, erase and write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter M25PE16 Read access allowed Device fully accessible time AI04009C Min. Max. 30 ...
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... M25PE16 8 Reset Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. All the lock bits are reset to 0 after a Reset Low pulse. Table 12 shows the status of the device after a Reset Low pulse. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω). 46/58 Table 13: Absolute maximum ratings Parameter (2) M25PE16 may Min. Max. Unit –65 150 °C ...
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... M25PE16 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... 0.9 MHz open / 0.9 MHz open – 0 –100 µA V –0.2 CC M25PE16 Max. Unit ± 2 µA ± 2 µA 50 µA 10 µ ...
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... M25PE16 Table 18. AC characteristics (50 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, WRSR f Clock frequency for read instructions R ( Clock high time CH CLH ...
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... C and Table 15 Min. Typ. Max. D. 100 8 8 100 0.8 3 (6) int(n/8) × 0.025 150 25 60 M25PE16 Unit MHz MHz µs µ ...
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... M25PE16 Figure 25. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 26. Write protect setup and hold timing W tWHSL High Impedance Q Figure 27. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHSH tCHDX tCLCH MSB IN tCH tCLQV DC and AC parameters tSHSL tSHCH tCHCL ...
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... Under completion of a WRSR operation Device deselected (S High) and in standby mode tSHRH tRLRH Table 14 and Table 15 Min. Typ Table 14 Table 15 and Min. Typ. Max. ( 300 t W Table 18 Table tRHSL AI06808b M25PE16 Max. Unit µs ns Unit µs µ (see or ms 19) 0 µs ...
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... M25PE16 12 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 29. VFQFPN8 (MLP8) 8-lead very thin dual flat package no lead, 6 × ...
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... Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.30 1.27 – – 0.10 0.00 0.60 0.50 0.75 12° 0.15 0.10 0.05 M25PE16 inches Typ Min Max 0.033 0.031 0.039 0.000 0.002 0.026 0.008 0.016 0.014 0.019 0.236 0.226 0.134 0.126 0.142 0.197 0.187 0.157 0.150 0.169 0.050 – – 0.004 0.000 0.024 0.020 0.029 12° 0.006 ...
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... M25PE16 Figure 30. SO8 wide – 8 lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 23. SO8 wide – 8 lead plastic small outline, 208 mils body width, mechanical ...
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... Option blank = standard packing T = tape and reel packing Plating technology ECOPACK® (RoHs compliant) For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 56/58 M25PE16 – M25PE16 T P ...
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... M25PE16 14 Revision history Table 25. Document revision history Date 16-Feb-2006 07-Aug-2006 13-Oct-2006 20-Nov-2006 12-Apr-2007 25-Mar-2008 01-Apr-2008 Revision 0.1 Initial release. Figure 3: Bus master and memory devices on the SPI bus and Note 2 added. Section 4.8.1: Protocol-related protections Address range for subsector 15 of sector 0 modified in Memory organization ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 58/58 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. M25PE16 ...