M25PE20-VMP6TP Numonyx, B.V., M25PE20-VMP6TP Datasheet
M25PE20-VMP6TP
Related parts for M25PE20-VMP6TP
M25PE20-VMP6TP Summary of contents
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... Deep Power-down mode 1 µA (typical) ■ Electronic signature – JEDEC standard two-byte signature (8012h for M25PE20, 8011h for M25PE10) – Unique ID code (UID) with 16 bytes read- only, available upon customer request only in the T9HX process ■ Software write protection on a 64-Kbyte sector basis ■ ...
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... A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 4.8.2 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 2/64 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15 M25PE20, M25PE10 ...
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... M25PE20, M25PE10 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Read Lock Register (RDLR 6.9 Page Write (PW 6.10 Page Program (PP 6.11 Write to Lock Register (WRLR 6.12 Page Erase (PE 6.13 SubSector Erase (SSE ...
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... Software protection truth table (sectors for M25PE20 or sectors for M25PE10, 64-Kbyte granularity Table 3. Protected area sizes for M25PE20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Protected area sizes for M25PE10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. M25PE20 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. M25PE10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9 ...
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... Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. M25PE20 block diagram Figure 7. M25PE10 block diagram Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. ...
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... Description 1 Description The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial paged Flash memories, respectively. They are accessed by a high speed SPI-compatible bus. The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction ...
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... M25PE20, M25PE10 Figure 1. Logic diagram - previous T7X process TSL Reset Table 1. Signal names Signal name (1) TSL or W Reset the previous T7X process the pin is a Top Sector Lock input whereas in the new T9HX process, the pin is a Write Protect input (see Figure 3 ...
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... V become read-only (protected from write, program and erase operations). When Top Sector Lock (TSL) is connected to V the other pages of memory. 8/64 , causing the top 256 pages (upper addresses) of the memory the top 256 pages of memory behave like CC M25PE20, M25PE10 ...
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... M25PE20, M25PE10 2.7 Write Protect (W) or Top Sector Lock (TSL) ● The Write Protect function is available in the T9HX process only (see note on page The Write Protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25PE20 or M25PE10 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high ...
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... M25PE20, M25PE10 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus ...
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... For optimized timings recommended to use the Page Write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few bytes (see characteristics (50 MHz operation, T9HX (0.11 µm) process) characteristics (75 MHz operation, T9HX (0.11 µm) 12/64 M25PE20, M25PE10 PW Page Write (PW), Table 23: AC and Table 24: AC process)) ...
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... M25PE20, M25PE10 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: ● when the designer is programming the device for the first time ● ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PE10 and M25PE20 feature the following data protection mechanisms: 4.8.1 Protocol-related protections ● Power On Reset and an internal timer (t changes while the power supply is outside the operating specification ● ...
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... M25PE20, M25PE10 4.8.2 Specific hardware and software protections The M25PE10/M25PE20 features a Hardware Protected mode, HPM, and two Software Protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. They are described below: HPM ● HPM in T7X process (see The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only ...
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... Operating features Table 2. Software protection truth table (sectors for M25PE20 or sectors for M25PE10, 64-Kbyte granularity) Sector Lock Register Lock Write Down bit Lock bit ● The second Software Protected mode (SPM2) uses the block protect (BP1, BP0, see Section 6 ...
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... Kbits, 4,096 bytes each) ● 2 sectors (512 Kbits, 65,536 bytes each) In the M25PE20 and M25PE10, each page can be individually: ● programmed (bits are programmed from ● erased (bits are erased from ● ...
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... Memory organization Table 6. M25PE10 memory organization Sector 1 0 18/64 Subsector 31 1F000h 16 10000h 15 0F000h 4 04000h 3 03000h 2 02000h 1 01000h 0 00000h M25PE20, M25PE10 Address range 1FFFFh 10FFFh 0FFFFh 04FFFh 03FFFh 02FFFh 01FFFh 00FFFh ...
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... M25PE20, M25PE10 Figure 6. M25PE20 block diagram Reset TSL Address Register 1. These features (in gray) are only available in the T7X process. High Voltage Control Logic I/O Shift Register and Counter 3FF00h 2FFFFh 00000h 256 bytes (page size) Memory organization Generator Status ...
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... These features (in gray) are only available in the T7X process. 20/64 High Voltage Control Logic I/O Shift Register and Counter 1FF00h FFFFh 00000h 256 bytes (page size) M25PE20, M25PE10 Generator Status 256 byte Register Data Buffer 1FFFFh Top 256 pages can be made read-only by using the TSL pin ...
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... M25PE20, M25PE10 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted into the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... Important note on page M25PE20, M25PE10 Addr Dummy Data bytes bytes bytes 06h 04h ...
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... M25PE20, M25PE10 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High ...
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... Page Erase (PE) instruction completion ● SubSector Erase (SSE) instruction completion ● Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 24/64 (Figure 9) resets the Write Enable Latch (WEL) bit Instruction D High Impedance Q M25PE20, M25PE10 AI03750D ...
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... M25PE20 and 11h for the M25PE10). The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes of the optional Customized Factory Data (CFD) content ...
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... Instructions Figure 10. Read Identification (RDID) instruction sequence and data-out sequence 1. The Unique ID code is available only in the T9HX process (see 26/64 M25PE20, M25PE10 Important note on page 6). ...
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... M25PE20, M25PE10 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Instructions Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 28/ Instruction Status Register Out MSB M25PE20, M25PE10 Status Register Out MSB 7 AI02031E ...
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... M25PE20, M25PE10 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Note: The Status Register BPi and SRWD bits are available in the T9HX process only. See Important note on page 6 Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable (WREN) instruction must previously have been executed ...
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... BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the SRWD, (HPM) BP1 and BP0 bits cannot be changed M25PE20, M25PE10 Important note on page Memory content (1) Protected area Unprotected area Protected against Ready to accept Page Program, Page Program and ...
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... Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence High Impedance Q 1. Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10. Figure 13 ...
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... C D High Impedance Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10. 32/64 , during the falling edge of Serial Clock (C). C Figure 14 ...
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... M25PE20, M25PE10 6.8 Read Lock Register (RDLR) Note: The Read Lock Register (RDLR) instruction is decoded only in the T9HX process (see Important note on page The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector (or subsector) ...
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... A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 34/64 Figure 16. Table 23: AC characteristics (50 MHz and Table 24: AC characteristics (75 MHz operation, M25PE20, M25PE10 ...
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... MSB 1. Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10 ≤ n ≤ 256 Instruction 24-bit address ...
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... A Page Program (PP) instruction applied to a page that is hardware protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 36/64 Figure 17. and Table 24: AC process)). M25PE20, M25PE10 Table 23: AC ...
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... MSB 1. Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10 ≤ n ≤ 256 Instruction 24-bit address ...
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... Instruction 24-bit address MSB Bit b7-b2 b1 Sector Lock Down bit value b0 Sector Write Lock bit value M25PE20, M25PE10 minimum value. SHSL Lock Register value MSB Value ‘ ...
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... Figure 19. Page Erase (PE) instruction sequence Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10. Figure 19 ...
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... Section 11: DC and AC Figure 20. SubSector Erase (SSE) instruction sequence Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10. 40/64 Table valid address for the SubSector Erase (SE) instruction. ...
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... Figure 21. Sector Erase (SE) instruction sequence Address bits A23 to A18 are ‘Don’t care’ in the M25PE20. Address bits A23 to A17 are ‘Don’t care’ in the M25PE10. or Table valid address for the Sector Erase (SE) instruction. Chip Figure 21 ...
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... Chip Select (S) Low. RHSL For the value of t RHSL AC parameters. Figure 22. Bulk Erase (BE) instruction sequence 42/64 Figure 22. see Table 26: Timings after a Reset Low pulse Instruction D M25PE20, M25PE10 Important note ) is initiated. While the BE Table 14: Device status after in Section 11: DC and AI03752D ...
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... M25PE20, M25PE10 6.16 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions ...
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... Figure 24. Release from Deep Power-down (RDP) instruction sequence 44/64 Figure 24 Instruction High Impedance Deep Power-down mode M25PE20, M25PE10 , the device is put in RDP t RDP Standby Power mode AI06807 ...
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... M25PE20, M25PE10 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at power-up, and then for a further delay ● power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included ...
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... These parameters are characterized only, over the temperature range –40 °C to +85 °C. 46/64 Program, Erase and Write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter M25PE20, M25PE10 Read access allowed Device fully accessible time AI04009C Min. Max. Unit ...
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... M25PE20, M25PE10 8 Reset Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. All the Lock bits are reset to ‘0’ after a Reset Low pulse. Table 14 shows the status of the device after a Reset Low pulse. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ® ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). 48/64 Table 15: Absolute maximum ratings Parameter (2) M25PE20, M25PE10 may Min. Max. Unit –65 150 °C (1) See note ° ...
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... M25PE20, M25PE10 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the devices. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... 0.1V / 0.9 MHz open C = 0.1V / 0.9 MHz open 1 –100 µA OH M25PE20, M25PE10 Min. Max. Unit ± 2 µA ± 2 µA 50 µA 10 µ – 0.5 0. 0. –0.2 ...
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... M25PE20, M25PE10 Table 21. AC characteristics (25 MHz operation) Symbol Alt ( CLH ( CLL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS t t CLQV CLQX HO t THSL ...
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... S High to Standby Power mode Page Write cycle time (256 bytes) Page Write cycle time (n bytes) Page Program cycle time (256 bytes) Page Program cycle time (n bytes) Page Erase cycle time Sector Erase cycle time . C M25PE20, M25PE10 (1) . and Table 17 Min. Typ. Max. Unit D ...
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... M25PE20, M25PE10 Table 23. AC characteristics (50 MHz operation, Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, WRSR f Clock frequency for READ instructions R ( Clock High time ...
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... When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 7. int(A) corresponds to the upper integer part of A. E.g. int(12/ int(32/ int(15.3) =16. 54/64 Table 16 Parameter 2 (peak to peak M25PE20, M25PE10 (1) (2) ) and Table 17 Min. Typ. Max. D. ...
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... M25PE20, M25PE10 Figure 27. Serial input timing S tCHSL C tDVCH D Q Figure 28. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold timing TSL or W tTHSL tWHSL High Impedance Q 1. For the differences between devices produced in the two processes, see ...
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... SE, BE, SSE, DP, RDP Under completion of an Erase or Program cycle of a PW, PP, PE, SE, BE operation Under completion of an Erase cycle of an SSE operation Under completion of a WRSR operation Device deselected (S High) and in Standby mode M25PE20, M25PE10 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449e ...
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... M25PE20, M25PE10 Figure 30. Reset AC waveforms S Reset tSHRH tRHSL tRLRH DC and AC parameters AI06808 57/64 ...
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... JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 31. SO8N – 8 lead Plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. 58/64 A ccc M25PE20, M25PE10 h x 45˚ c 0.25 mm GAUGE PLANE SO-A ...
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... M25PE20, M25PE10 Table 27. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc millimeters Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4.80 5.00 6.00 5.80 6.20 3.90 3.80 4.00 1.27 – – 0.25 0.50 0° 8° 0.40 1.27 1.04 Package mechanical inches Typ Min Max 0.069 0.004 0.010 ...
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... Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.30 1.27 – – 0.10 0.00 0.60 0.50 0.75 12° 0.15 0.10 0.05 M25PE20, M25PE10 aaa ddd C inches Typ Min 0.033 0.031 0.000 0.026 0.008 0.016 0.014 0.236 0.226 0.134 0.126 0.197 0.187 0.157 0.150 0.050 – 0.004 0.000 0.024 0.020 70-ME Max 0.039 0.002 ...
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... M25PE20, M25PE10 13 Ordering information Table 29. Ordering information scheme Example: Device type M25PE = Page-erasable serial Flash memory Device function Mbit (128 Mbit (256 Operating voltage 2 3 Package MN = SO8N (150 mil width VFQFPN8 6 × (MLP8) Device grade 6 = Industrial: device tested with standard test flow over – ...
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... At power-up the WIP bit is reset and the Lock Registers are reset (see Section 7: Power-up and power-down). V max changed in Table 15: Absolute maximum IO M25PE20 and M25PE10 products processed in T9HX process added to 3 datasheet: – WP pin replaces TSL (T7X technology), see (W) or Top Sector Lock (TSL) – Read Lock Register ...
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... M25PE20, M25PE10 Table 30. Document revision history (continued) Date Version 30-Jan-2008 20-Mar-2008 Removed ‘low voltage’ from the title. Updated the value for the maximum clock frequency (from MHz) through the document. Added: Table 20: DC characteristics (T9HX (0.11 µ characteristics (75 MHz operation, T9HX (0.11 µm) process) ECOPACK® ...
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... Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 64/64 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. M25PE20, M25PE10 ...