T8531 Agere Systems, Inc., T8531 Datasheet
T8531
Related parts for T8531
T8531 Summary of contents
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... Serial microcontroller control interface Available in 64-pin MQFP and TQFP packages General Description The Multichannel Programmable Codec Chip Set is comprised of the T8531 16-channel line card signal processor and one or two custom T8532 octal A/D and D/A converters. A ROM-coded tone plant is included on the signal processor. Together these devices achieve a highly integrated and highly pro- grammable multichannel voice codec solution ...
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... The DSP Engine ac Path Coefficient Table ........ 17 The Time-Slot Control Word................................ 18 Operations Performed by the DSP Engine at T8531 Start-Up ................................................. 18 Microprocessor Start-Up of the DSP Engine....... 19 Powering Up a Time Slot in the T8531................ 19 Disabling a Time Slot in the T8531 ..................... 19 T8532 Powerup/Powerdown ............................... 19 Changing DSP RAM Space of an Active Time Slot........................................................... 20 DSP Engine Memory Requirements ...
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... Table 35. Bits 15:9 of T8531 Board Control Word 2 at 0x1FFC..................................................40 Table 36. Bits 8:0 of T8531 Board Control Word 2 at 0x1FFC..................................................40 Table 37. Bits 15:0 of T8531 Board Control Word 3 at 0x1FFA ..................................................40 Table 38. Bits 15:0 of T8531 Board Control Word 4 at 0x1FF8 ..................................................40 Table 39. Bits 15:0 of T8531 Board Control Word 5 at 0x1FF6 ..................................................40 Table 40. Bits 15:0 of T8531 Reset of Microprocessor Commands at 0x7FFF .....40 Table 41 ...
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... A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T8531. Another serial interface accepts control data from the T8531 for activating the various gain settings, self-test, and powerdown modes ...
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... T8531 Description As shown in Figure 4, the T8531 contains a digital signal processor (DSP) engine surrounded by a customized input/output frame. The I/O frame performs the -law or A-law conversion as well as the decimation and interpola- tion functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The sigma- delta converters operate ...
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... Figure 6. Control, PCM, and Octal Interfaces 6 REL REL ABS ABS RDG RDG RDG RDG BALANCE BALANCE FILTER FILTER REL TDG Figure 5. T8531 Digital ac Path OCTAL INTERFACE T8531 8 kHz SYNC OSFS UPCK 4 MHz CLOCK OSCK UPCS DATA OSDR0 UPDI OSDR1 DATA UPDO ...
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November 2000 Pin Information 64 63 VRTX7 1 VRP7 2 VRN7 SSA VRN6 5 VRP6 6 VRTX6 7 VTX6 DDA VTX5 10 VRTX5 11 VRP5 12 VRN5 SSA VRN4 15 VRP4 ...
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... T8531 through each of these pins. The data rate is 4.096 MHz. Oversampled Receive Data. Four channels of 1.024 MHz - receive data is received from the T8531 on each of these pins. The data rate is 4.096 MHz. Interface Clock. The 4.096 MHz clock that enters this pin from the T8531 serves as the bit clock for all the oversampled data transmission between this chip and the T8531 ...
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... SSA Lucent Technologies Inc T8531 Figure 8. T8531 64-Pin TQFP Codec Chip Set JTESTB OSDX2 44 OSDR2 43 OSDX3 42 OSDR3 OSFS 39 OSCK ...
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... MHz SCK. An internal pull-up device is included, pro- viding 4.096 MHz SCK operation with no external connections. Receive PCM Input. The data on this pin is shifted into the T8531 on the falling edges of SCK. Data is only entered for valid time slots as defined in the TSA registers ...
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... TSTCLK to drive the chip. A pull-up device is provided MHz Clock Output. 16.384 MHz clock output (50% duty cycle). Note that this clock divides down to a lower frequency (dependent upon the DSPCKSL setting) when the T8531 is in hardware reset. The frequency of CK16 is unaffected by software reset. CI Test Clock. ...
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... The signal level to produce a 0 dBm0 level at the digital transmit output of the T8531 is not a fixed quantity as explained above. For a line with a complex impedance echo signal, extra headroom must be allowed and the TX signal level must be set to account for the headroom ...
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... The gain values are shown in Table 26; gain tolerances are 2%. Differential receive output is assumed. Digital Termination Impedance Synthesis The CTZ filter in the T8531 synthesizes complex termi- nation impedances. The CTZ filter utilizes alpha and beta coefficients (board control words 4 and 5, respec- tively) to perform the synthesis. One set of alpha beta coefficients is required for each termination impedance and balance network ...
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... ACT register (table 29). Unlike the ACT register, this digital loopback mode is selectable per channel. This loop- back mode can be used to check T8532 functionality from the T8531 device also used during the cali- bration sequence There is one loopback mode in the T8531 ...
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... MHz. Microprocessor interface com- mands consist of two words, address and data. Address and data are 16 bits wide. The T8531 expects an address first. The first bit of the address word is the R/W flag, which tells the T8531 whether it must receive or send data (receive, R ...
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... The data rate of 2.048 MHz allows 256 SCK cycles in a frame, i.e., eight address/data pairs with no pause between words. Since the DSP engine can process only one interrupt every 7.8 s, the T8531 requires a separation between address and data on read and write instructions to the microprocessor interrupt (see Figure 10) ...
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... RAM location in the DSP engine and to write to specified addresses. The DSP Engine Time-Slot Information Tables In the T8531, the DSP engine RAM has been set up to contain 16 tables which hold the pointers to the ac coefficients and data buffers required to process each time slot ...
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... Operations Performed by the DSP Engine at T8531 Start-Up The DSP engine performs its start-up code after it has been reset. All interrupts are disabled. First, the DSP engine computes the checksum for its ROM and RAM to verify their integrity. Next, the DSP engine walks through each time-slot information table and sets the data buffer and coefficient pointers ...
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... BCW2 (0x1FFC). This flags the TSA control to start normal operation. Powering Up a Time Slot in the T8531 Depending on the application, the microprocessor may choose to set up the ac coefficients for a channel just prior to enabling it for use. This requires 16 micropro- ...
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... The DSP engine firmware is ROM based. The hard- ware development system code is also ROM based. The DSP engine ROM memory map is given in Table 41. Table 7. Summary of Microprocessor Commands for Control of T8531 Data Processing Function Required Bulk TSA register download & BCW2 Individual TSA register download ...
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... Alternatively, the T8532s can be reset through software reset (Tables 21 and 22), which is generated by the external controlling device and routed to the T8532s via the T8531. This can only occur when OSCK is guaranteed to be valid, i.e., not within power- on hardware reset. Lucent Technologies Inc. ...
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... A bit is set high for every failed (continued) channel. The preceding section discussed the sequence of instructions that must be followed in order to properly configure the T8531 for normal operation. The auto- calibration procedure is mandatory after hardware reset. Tone Plant The following tone plant functions are provided in ROM code in the T8531 device ...
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... CDM. A standard HBM (resistance = 1500 accepted and can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Device Voltage (V) T8531 T8532 Lucent Technologies Inc. Symbol ...
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Codec Chip Set Electrical Characteristics For all specifications – + and Input signal frequency is 1020 Hz, unless otherwise noted. DSP clock frequency is A ...
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... Absolute GAL Levels (T8532 TX gain = 0 dB; T8531 gain = –1.65 dB) (T8532 RX gain = 6.02 dB; T8531 gain = 0.21 dB) (T8532 TX gain =12.04 dB; T8531 gain = –1.65 dB) (T8532 RX gain = –12.04 dB; T8531 gain = 0.21 dB) Transmit Gain GXA Absolute 0 dBm0 test level, measured deviation of digital code Accuracy from ideal 0 dBm0 level at OSDX[1:0] digital outputs, ...
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Codec Chip Set Transmission Characteristics Table 12. Gain and Dynamic Range (continued) Parameter Symbol Transmit Gain Variation GXAF with Frequency Transmit Gain Variation GXAL with Signal Level Receive Gain Absolute GRA Accuracy Relative Gain: — VRP to VRN Relative Phase: ...
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November 2000 Transmission Characteristics Table 13. Noise (per Channel) Parameter Symbol Transmit Noise C-message Weighted Transmit Noise P-message Weighted Receive Noise C-message Weighted Receive Noise P-message Weighted Noise, Single Frequency N RS ...
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Codec Chip Set Transmission Characteristics Table 14. Distortion and Group Delay Parameter Symbol Signal to Total Distortion Transmit or Receive C-message Weighted Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion TX Group Delay, Absolute RX Group Delay, Absolute ...
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November 2000 Timing Characteristics A signal is valid above V or below V IH ification, the following conditions apply: All input signals are defined measured from measured ...
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Codec Chip Set Timing Characteristics (continued) TIME SLOT tFSHFSL SFS tSFHSCL tSCLSFL SCK tSCHDXV SDX † SDR Card address 0, bit offset 0 assumed. † ...
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November 2000 Timing Characteristics (continued) Table 17. Serial Control Port Timing (See Figure 10.) Symbol Parameter tCSHLSET UPCS to UPCK Setup tCSLHHOD UPCS to UPCK Hold tUPDIST UPDI to UPCK Setup tUPDIHD UPDI to UPCK Hold tUPDODEL UPCK to UPDO ...
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... Codec Chip Set Software Interface Table 18 lists the RAM data space for the DSP engine. Space for channels is allocated. The total T8531 RAM size is 4 Kwords, arranged Kbanks. Address bit 15 is used as a read/write flag (1 = read). The micro- processor interface can read any address in the DSP engine RAM space ...
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November 2000 Software Interface (continued) Table 18. DSP Engine RAM Memory Map (continued) Address Range 0x04B5 Channel 8 ac filter coefficients 0x04C5 Channel 9 ac filter coefficients 0x04D5 Channel 10 ac filter coefficients 0x04E5 Channel 11 ac filter coefficients 0x04F5 ...
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... Table 20A. Bit Map for T8531 Time-Slot Assignment Registers at 0x1400—0x140F 15—6 5 Not used CTZ disable Null channel Table 20B. Bit Map for CTZ Disable and Null Channel Bit 5 Bit ...
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... Channel 4 control register 2 0x151D Channel 5 control register 2 0x151E Channel 6 control register 2 0x151F Channel 7 control register 2 Lucent Technologies Inc. Table 22. T8531 Channel Register Memory Map for T8532 Device 1 All registers can be written by the microprocessor interface. Address Memory Range Contents 0x1540 Channel 8 powerup/powerdown register ...
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Codec Chip Set Software Interface (continued) Table 24. Bit Map for T8532 Channel Control Register 1 at 0x1508—0x150F and 0x1548—0x154F 15 14—8 7 PWR Not used Table 25. T8532 Control Register 1: Transmit Gain Bit 7 Bit 6 TXGAIN2 TXGAIN1 ...
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November 2000 Software Interface (continued) Table 27. T8532 Control Register 1: Digital Loopback Bit 0 LPBK 0 1 Table 28. Bit Map for T8532 All Channel Test Register at 0x1510 and 0x1550 15—4 3 Not used Read out address Table ...
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... Table 32. T8531 Control Register Map Address Range 0x1FFE 0x1FFC 0x1FFA 0x1FF8 0x1FF6 Note: A board control word controls a function that is common to all 16 channels of a given chip set. 38 Bit Number and Function 6—3 2 Not used Receive gain ...
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... Table 34. Bits 7:0 of T8531 Board Control Word 1 at 0x1FFE Bit Number — — — — — — — — ...
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... Table 38. Bits 15:0 of T8531 Board Control Word 4 at 0x1FF8 Bit Number and Function 15—10 Not used Note: The default value after hardware reset or powerup is A4. Table 39. Bits 15:0 of T8531 Board Control Word 5 at 0x1FF6 Bit Number and Function 15—8 Not used Note: The default value after hardware reset or powerup is 0. ...
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November 2000 Software Interface (continued) Table 41 shows the memory map for the DSP engine ROM. The ROM information is not accessible via the micro- processor. The total ROM size is 8 Kwords. Table 41. DSP Engine ROM Memory Map ...
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... Codec Chip Set Applications Figure 11 shows a full line card implementation using the T8531/T8532 codec and the L7585 SLIC with inte- grated relays. One T8531 and two T8532 devices sup- port 16 SLIC devices (only one L7585 SLIC is illustrated). Figure 11 portrays only the transmission paths inside the L7585 SLIC ...
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November 2000 Applications (continued) Figure 12 shows the complete SLIC schematic for interfacing to the Lucent L9215G short-loop, sine wave, ringing SLIC. All ac parameters are programmed by the codec. Note this codec differentiates itself in that no external com- ...
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Codec Chip Set Applications (continued) Figure 13 shows the complete SLIC schematic for interfacing to the Lucent L9310G Line Interface and Line Access circuit. All ac parameters are programmed by the codec. Note this codec differentiates itself in that no ...
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... VTX is a high-impedance input. The R provide the necessary bias for the VTX inputs – 1. 1/2 LM2904 OR EQUIVALENT Figure 14. Common 2.4 V Voltage Reference Codec Chip Set VREFx VRTX15 VRTX1 VRTX0 R VREF0 TO VTX0 301 k T8531 VREF1 0 VTX1 301 k R VREF15 VTX15 301 k resistors 12-3570 (F)x 45 ...
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Codec Chip Set Outline Diagrams 64-Pin MQFP 1 16 DETAIL A 1.60 REF GAGE PLANE SEATING PLANE 46 17.20 0.25 14.00 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 2.55/2.75 0.80 TYP 0.25 MAX 0.25 0.30/0.45 0.73/1.03 ...
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November 2000 Outline Diagrams (continued) 64-Pin TQFP DETAIL A 0.50 TYP 0.19/0.27 DETAIL B Lucent Technologies Inc. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE 49 48 10.00 0. DETAIL B 1.40 0.05 1.60 ...
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Codec Chip Set Ordering Information Device Code T-8531 - - - TL-DB 64-Pin TQFP, Dry pack tray T-8531 - - - TL-DT 64-Pin TQFP, Dry-bagged, Tape & Reel T-8532 - - - JL-DB 64-Pin MQFP, Dry pack tray T-8532 - ...