IC BUFFER HEX NON-INVERT 16SOIC

MC14050BDR2G

Manufacturer Part NumberMC14050BDR2G
DescriptionIC BUFFER HEX NON-INVERT 16SOIC
ManufacturerON Semiconductor
Series4000B
MC14050BDR2G datasheet
 

Specifications of MC14050BDR2G

Logic TypeBuffer/Line Driver, Non-InvertingNumber Of Elements6
Number Of Bits Per Element1Current - Output High, Low10mA, 40mA
Voltage - Supply3 V ~ 18 VOperating Temperature-55°C ~ 125°C
Mounting TypeSurface MountPackage / Case16-SOIC (3.9mm Width)
Logic FamilyMC140Number Of Channels Per ChipHex
PolarityNon-InvertingSupply Voltage (max)18 V
Supply Voltage (min)3 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTHigh Level Output Current- 4.7 mA (Min)
Input Bias Current (max)4 uALow Level Output Current30 mA (Min)
Minimum Operating Temperature- 55 CPropagation Delay Time140 ns @ 5 V or 80 ns @ 10 V or 60 ns @ 15 V
Number Of Lines (input / Output)6 / 6Logic Device TypeBuffer, Non Inverting
Supply Voltage Range3V To 18VLogic Case StyleSOIC
No. Of Pins16Operating Temperature Range-55°C To +125°C
Filter TerminalsSMDRohs CompliantYes
Family Type4000 CMOSLead Free Status / RoHS StatusLead free / RoHS Compliant
Other namesMC14050BDR2GOS
MC14050BDR2GOS
MC14050BDR2GOSTR
  
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MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, V
The input−signal high level (V
IH
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
v 0.4 V, I
≥ 3.2 mA).
(V
= 5.0 V, V
DD
OL
OL
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
Features
High Source and Sink Currents
High−to−Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
V
can exceed V
IN
DD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
Input Voltage Range (DC or Transient)
in
V
Output Voltage Range (DC or Transient)
out
I
Input Current (DC or Transient) per Pin
in
I
Output Current (DC or Transient) per Pin
out
P
Power Dissipation, per Package (Note 1)
D
(Plastic)
(SOIC)
T
Ambient Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature (8−Second Soldering)
L
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the V
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
≤ V
≤ 18 V and V
≤ V
≤ V
ranges V
SS
in
SS
out
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
or V
). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
.
DD
) can exceed the V
supply
DD
)
SS
Value
Unit
−0.5 to +18.0
V
−0.5 to +18.0
V
−0.5 to V
+
V
DD
0.5
± 10
mA
± 45
mA
mW
825
740
°C
−55 to +125
°C
−65 to +150
°C
260
pin only. Extra
SS
are recommended.
DD
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
MC140xxBCPG
P SUFFIX
AWLYYWW
CASE 648
1
16
SOIC−16
140xxBG
D SUFFIX
AWLYWW
CASE 751B
1
16
TSSOP−16
0xxB
DT SUFFIX
ALYW
CASE 948F
1
16
SOEIAJ−16
MC140xxB
F SUFFIX
ALYWG
CASE 966
1
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14049B/D
14

MC14050BDR2G Summary of contents

  • Page 1

    ... Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev can exceed the V ...

  • Page 2

    ... MC14049BDG MC14049BDR2 MC14049BDR2G MC14049BFEL MC14050BCP MC14050BCPG MC14050BD MC14050BDR2 MC14050BDR2G MC14050BDT MC14050BDTR2 MC14050BFEL MC14050BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MC14049B, MC14050B ...

  • Page 3

    ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

  • Page 4

    AC SWITCHING CHARACTERISTICS (Note 5) Î Î ...

  • Page 5

    Figure 3. Ambient Temperature Power Derating PULSE GENERATOR Invert on MC14049B only Figure 4. ...

  • Page 6

    0.25 (0.010) M −A− −B− −T− SEATING PLANE 0.25 (0.010 MC14049B, MC14050B PACKAGE ...

  • Page 7

    K 16X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) SEATING −T− PLANE D MC14049B, MC14050B PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX PLASTIC ...

  • Page 8

    ... DETAIL P VIEW American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...