A45L9332A Series AMIC Technology, Corp., A45L9332A Series Datasheet
A45L9332A Series
Related parts for A45L9332A Series
A45L9332A Series Summary of contents
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... X 32Bit X 2 Banks Synchronous Graphic RAM Revision History Rev. No. History 0.0 Initial issue 0.1 Update AC and DC data specification PRELIMINARY (October, 2001, Version 0.1) 256K X 32 Bit X 2 Banks Synchronous Graphic RAM A45L9332A Series Issue Date Remark August 21, 2001 Preliminary October 22, 2001 AMIC Technology, Inc. ...
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... Write Per Bit (Old Mask) n Block Write (8 Columns) frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphics system. 1 A45L9332A Series AMIC Technology, Inc. ...
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... VSSQ VDDQ 22 DQM 23 0 DQM CAS RAS BA(A10 PRELIMINARY (October, 2001, Version 0.1) A45L9332AE A45L9332AF 2 A45L9332A Series VDDQ VSSQ VDDQ VSSQ ...
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... Version 0.1) WRITE CONTROL MUX LOGIC 256K x 32 256K x 32 CELL ARRAY ROW DECORDER BANK SELECTION ROW COLUMN ADDRESS ADDRESS BUFFER BUFFER ADDRESS REGISTER CLOCK ADDRESS (A0~A10) 3 A45L9332A Series MASK REGISTER CLOCK REGISTER DQMi CELL ARRAY REFRESH COUNTER AMIC Technology, Inc. DQi (i=0~31) ...
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... Blocks data input when DQM active. (Byte Masking) Data inputs/outputs are multiplexed on the same pins. Enables write per bit, block write and special mode register set. Power Supply: +3.3V 0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 4 A45L9332A Series AMIC Technology, Inc. ...
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... DQ0 to DQ15 Symbol Min Typ 3.0 3.3 V 2 5ns). VDD Symbol C DC1 C DC2 5 A45L9332A Series Min Typ 2 2 CAS Max Unit 3.6 V VDD+0 See Figure 1 Value 0.1 + 0.01 0.1 + 0.01 AMIC Technology, Inc. Max Unit ...
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... Input signals are stable 0mA, Page Burst OL All bank Activated (min) CCD CCD t t (min CKE 0. (min), I =0mA, t (min BWC 6 A45L9332A Series Speed CAS Latency - 230 210 170 2 - 260 160 15ns 15ns ...
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... See Fig.2 V (DC) = 2.4V -2mA (DC) = 0.4V 2mA OL OL 3pF -6 CAS Latency Min Max 3 6 1000 5 2 A45L9332A Series V =1. =50 OUTPUT O 30pF (Fig Output Load Circuit -7 -8 Unit Min Max Min Max 7 8 1000 1000 6 7 2.5 2 ...
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... PRELIMINARY (October, 2001, Version 0. CAS Latency Min Max Min 3 2 *All AC parameters are measured from half to half. 8 A45L9332A Series -8 Unit Note Max Min Max - 2 6 AMIC Technology, Inc ...
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... CAS to CAS delay at block write cycle only. 9 A45L9332A Series Version Unit Note - CLK CLK CLK CLK 100 ...
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... Valid Don’t Care Logic High Logic Low) 10 A45L9332A Series DSF DQM A10 A9 A8~A0 Notes CODE Row Addr Column H ...
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... SDRAM = Graphic Memory + main Memory PRELIMINARY (October, 2001, Version 0.1) after the end of burst. PR Bank Active H L Bank Active Bank Active with SMRS Write per bit Write per bit Disable 11 A45L9332A Series Write H L Normal with Write Enable AMIC Technology, Inc. H Block Write ...
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... Reserved Reserved Reserved Reserved Load Color Load Mask A6 Function A5 Function 0 Disable 0 Disable 1 Enable 1 12 A45L9332A Series Burst Length Burst Length Type BT=0 Sequential Interleave ...
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... Byte I/O – I DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 13 A45L9332A Series Interleave Interleave ...
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... And the write burst length is programmed using A9. A7~A8 and A10 must be set to low for normal SGRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies. 14 A45L9332A Series CAS and and DSF (The SGRAM should be in active , WE ...
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... The minimum number of clock cycles required to complete row precharge is calculated by dividing “t time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge 15 A45L9332A Series CS , CAS ” after the last data input to be RDL ...
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... DQ’s are idle write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can obtained by referring corresponding timing diagram. 16 A45L9332A Series CS , RAS , CAS and CKE with high ” ...
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... DQM masking provides independent data byte masking during block write exactly the same as it does during normal write operations, except that the control is extended to the consecutive 8 columns of the block write. PRELIMINARY (October, 2001, Version 0.1) A45L9332A Series Timing Diagram to Illustrate t BWC 0 1 Clock ...
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... Write-per-bit capability (bit plane masking). A and B banks share. DQM0-3 Byte masking (pixel masking for 8bpp system) for data-out/in Each bit of the mask register directly controls a corresponding bit plane. 2) Clock Suspended During Read (BL= A45L9332A Series Benefits Masked by CKE Suspended Dout ...
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... Each DQMi masks 8 DQi’s. (1 Byte, 1 Pixel for 8bbp). 2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. PRELIMINARY (October, 2001, Version 0.1) 2) Read Mask (BL=4) RD Hi-Z Hi Hi-Z Hi A45L9332A Series Masked by CKE Hi Hi DQM to Data-out Mask = 2 Hi ...
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... QB2 QB3 CCD Note2 C D Note4 DC0 DQ(CL2) Pixel t CDL DQ(CL3) Note3 CAS access; read, write and block write. 20 A45L9332A Series 3) Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 Pixel DA0 QB0 t CDL Note3 AMIC Technology, Inc. QB1 ...
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... To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. PRELIMINARY (October, 2001, Version Note Hi Hi Note 2 21 A45L9332A Series AMIC Technology, Inc. ...
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... Q3 2) Block Write CLK CMD D2 D3 (CL 2,3) Note 3 Auto Precharge Starts Note 3 Auto Precharge Starts interrupt of the same/another bank is illegal. CAS 22 A45L9332A Series BW PRE Pixel t BPL Note Pixel BPL Note 3 Auto Precharge Starts AMIC Technology, Inc. ...
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... D3 t Note 1 RDL 4) Read Burst Stop (Full Page Only) PRE Note DQ(CL2 DQ(CL3) 2) Special Mode Register Set MRS ACT t 1CLK RP 23 A45L9332A Series CLK CMD WR STOP BDL CLK CMD RD STOP CLK CMD SMRS ACT SMRS ...
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... Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended. PRELIMINARY (October, 2001, Version 0.1) 2) Power Down (=Precharge Power Down) Exit t SS Internal A45L9332A Series CLK CKE t SS Note 2 CLK NOP ACT CMD Note 5 CMD CMD t RC AMIC Technology, Inc. ...
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... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 25 A45L9332A Series CAS interrupt can not be issued. AMIC Technology, Inc. ...
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... Blue White White Green Blue Green Blue Green Blue White White Green 26 A45L9332A Series DQM1=0 DQM0 ...
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... Blue Yellow Blue Blue Blue Blue Blue Blue Blue Yellow Blue PIXEL MASK I/O MASK 27 A45L9332A Series (Pixel Mask Yellow Red DQM1=0 DQM0 Green ...
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... DQM High level is necessary High-Z DQ Precharge Auto Refresh (All Banks) PRELIMINARY (October, 2001, Version 0. Auto Refresh 28 A45L9332A Series KEY KEY KEY Mode Regiser Set AMIC Technology, Inc Row Active (Write per Bit ...
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... SAC SLZ SHZ Write or Block Write 29 A45L9332A Series *Note 4 *Note *Note 3 *Note 4 Rb *Note 5 Qc Row Active Read (Write per Bit Enable or Precharge Disable AMIC Technology, Inc ...
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... Bank A row active, enable write per bit function for bank A L Bank B row active, disable write per bit function for bank B H Bank B row active, enable write per bit function for bank B Operation Minimum cycle time Normal write t Block write t 30 A45L9332A Series CCD BWC AMIC Technology, Inc. ...
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... OH Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD 31 A45L9332A Series Cb0 Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write (A-Bank) SAC AMIC Technology, Inc ...
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... High Cb0 Cc0 *Note 2 *Note1 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Dc0 Write Read (A-Bank) (A-Bank) before Row precharge, will be written. RDL 32 A45L9332A Series *Note 2 Cd0 t RDL t CDL *Note3 Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 Write ...
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... Version 0. High CAb RBa CBa RBa Pixel Pixel Mask Mask Row Active (B-Bank) Block Write (B-Bank) 33 A45L9332A Series CBb Pixel Mask Block Write with Auto Precharge (B-Bank) AMIC Technology, Inc Don't care ...
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... RBa CAa Pixel I/O DBa0 DBa1 Color Mask Mask Row Active Load Color with WPB* Register Enable Masked Write (B-Bank) with Auto Precharge Load Mask Register (B-Bank) 34 A45L9332A Series DBa2 DBa3 WPB* : Write-Per-Bit AMIC Technology, Inc Don't care ...
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... QBb0 QBb1 QAa0 QAa1 QAa2 QAa3 QBb0 Read (B-Bank) WE CAS RAS , and are high at the clock high going edge. 35 A45L9332A Series CAc CBd CAe QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 ...
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... Version 0. High RBb CBb RBb t CDL DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 Write (B-Bank) 36 A45L9332A Series CAc CBd DAc2 DAc3 DBd0 DBd1 Masked Write Write with auto with auto Precharge precharge (B-Bank) (A-Bank) AMIC Technology, Inc ...
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... High RBb RBb QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Precharge (A-Bank) Row Active (B-Bank) 37 A45L9332A Series CBb RAc CAc RAc t CDL *Note 1 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write Read (B-Bank) ...
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... Version 0. High CAa QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Auto Precharge Start Point (A-Bank) 38 A45L9332A Series CBb DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write with Auto Precharge Auto Precharge (B-Bank) AMIC Technology, Inc ...
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... Qb0 Qb1 Qb2 Qa0 Qa1 Qb0 Qb1 Read without Auto Precharge (B-Bank) Auto Precharge Strart Point (A-Bank) *Note 1 after A Bank auto precharge starts A45L9332A Series Qb3 Qb2 Qb3 Precharge Row Active (B-Bank) (A-Bank) AMIC Technology, Inc. ...
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... Rb Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 * Note 1 Read with Auto Precharge Start Point Auto Precharge (B-Bank) (A-Bank) Row Active (B-Bank) 40 A45L9332A Series Qb0 Qb1 Qb2 Qb3 Qb0 Qb1 Db2 Db3 Auto Precharge Start Point (B-Bank) AMIC Technology, Inc. ...
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... Note 1 * Note 2 1 QAa1 QAa2 QAa3 QAa4 QAa0 2 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank) 41 A45L9332A Series QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Precharge (A-Bank) RAS interrupt. AMIC Technology, Inc. 18 ...
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... Version 0. High CAb * Note 1 t BDL * Note 2 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 Write Burst Stop (A-Bank) 42 A45L9332A Series RDL * Note 3 DAb4 DAb5 AMIC Technology, Inc Precharge (A-Bank) : Don't care ...
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... High RBb CAb RBb QAb0 QAb1 QAb0 QAb1 Row Active (A-Bank) (B-Bank) Read with Auto Precharge (A-Bank) 43 A45L9332A Series Note 2 RAc CBc CAd RAc DBc0 QAd0 QAd1 DBc0 QAd0 Read (A-Bank) Write with Auto Precharge (B-Bank) AMIC Technology, Inc ...
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... Read Suspension * Note : 1. DQM needed to prevent bus contention. PRELIMINARY (October, 2001, Version 0. Qa0 Qa1 Qa2 Qa3 t SHZ Clock Read 44 A45L9332A Series Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write DQM Read DQM Clock Write Suspension AMIC Technology, Inc ...
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... Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command A45L9332A Series Qa0 Qa1 Qa2 Read Precharge AMIC Technology, Inc Don't care ...
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... If the system uses burst refresh. PRELIMINARY (October, 2001, Version 0. Note 4 * Note 3 Hi-Z Self Refresh Exit 46 A45L9332A Series min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Inc. ...
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... Please refer to Mode Register Set table. PRELIMINARY (October, 2001, Version 0.1) Auto Refresh Cycle Auto Refresh WE activation and DSF of low at the same clock cycle with address key will set internal RAS activation. 47 A45L9332A Series High t RC Hi-Z AMIC Technology, Inc ...
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... Term burst; Block Write; Latch CA; Determine ILLEGAL Term Burst; Precharge timing for Reads ILLEGAL ILLEGAL 48 A45L9332A Series Action Row Active) Row Active) Row Active AMIC Technology, Inc. Note ...
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... NOP Idle after NOP Idle after ILLEGAL CA,AP ILLEGAL ILLEGAL NOP Idle after ILLEGAL 49 A45L9332A Series Action Row Active AMIC Technology, Inc. Note ...
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... NOP Idle after NOP Idle after ILLEGAL ILLEGAL ILLEGAL BA = Bank Address (A10 Column Address (A0~A7) 50 A45L9332A Series Action Note BWC BWC RCD RCD Precharge All (A9 Auto Precharge (A9) AMIC Technology, Inc ...
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... A45L9332A Series Action INVALID Exit Self Refresh ABI after t RC Exit Self Refresh ABI after t RC ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL ...
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... LQFP (Height = 1.4mm Max) PRELIMINARY (October, 2001, Version 0.1) Clock Frequency (MHz) 6 166 6 166 7 143 7 143 8 125 8 125 52 A45L9332A Series Access Time Package 5 100 QFP 5 100 LQFP 6 100 QFP 6 100 LQFP 6 100 QFP 6 100 LQFP AMIC Technology, Inc. ...
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... L 0.025 0.031 0.037 0.650 L 0.057 0.063 0.069 1.450 0.004 - A45L9332A Series unit: inches/ Dimensions in mm Nom. Max 2.85 2.977 - 0.36 0.150 0.158 23.200 23.450 20.000 20.100 17.200 17.450 14.000 14.100 0.650 ...
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... E 0.783 0.787 0.791 19.90 0.624 0.630 0.636 15.85 D 0.547 0.551 0.555 13.90 0.026 BSC 0.018 0.024 0.030 0.45 0.039 REF 0.004 - 0 3 A45L9332A Series unit: inches/ Nom. Max 1.40 1.45 0.32 0.37 - 0.20 22.00 22.15 20.00 20.10 16.00 16.15 14.00 14.10 0.65 BSC 0.60 0.75 1.00 REF - 0.1 3.5 7 AMIC Technology, Inc. ...