A45L9332F-10 AMIC Technology, Corp., A45L9332F-10 Datasheet
A45L9332F-10
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A45L9332F-10 Summary of contents
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Preliminary Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History Rev. No. History 0.0 Initial issue PRELIMINARY (December, 1998, Version 0.0) 256K X 32Bit X 2 Banks Synchronous Graphic RAM A45L9332 Series Issue Date Remark December ...
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Preliminary Features n JEDEC standard 3.3V power supply n LVTTL compatible with multiplexed address n Dual band / Pulse RAS n MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst ...
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Pin Configuration VDDQ VSSQ VDDQ VSSQ VDDQ VDD ...
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Block Diagram DQMi BLOCK WRITE CONTROL LOGIC CLK CKE COLUMN MASK CS RAS CAS WE DSF DQMi SERIAL COUNTER PRELIMINARY (December, 1998, Version 0.0) WRITE CONTROL MUX LOGIC 256K x 32 256K x 32 CELL ARRAY ROW DECORDER BANK SELECTION ...
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Pin Descriptions Symbol Name CLK System Clock Chip Select CS CKE Clock Enable A0~A9 Address A10(BA) Bank Select Address Row Address Strobe RAS Column Address Strobe CAS Write Enable WE DQMi Data Input/Output Mask DQi Data Input/Output DSF Define Special ...
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Absolute Maximum Ratings* Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DC Electrical Characteristics (Recommended operating condition unless otherwise noted, T Symbol Parameter Operating Current I cc1 (One Bank Active Precharge Standby cc2 Current in power down mode cc2 I N CC2 Precharge Standby Current in non ...
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AC Operating Test Conditions (VDD = 3.3V 0.3V + Parameter AC input levels Input timing measurement reference level Input rise and all time (See note3) Output timing measurement reference level Output load condition ...
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AC Characteristics (continued) (AC operating conditions unless otherwise noted) Symbol Parameter t CLK low pulse width CL t Input setup time SS t Input hold time SH t CLK to output in Low-Z SLZ CLK to output CAS Latency = ...
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Operating AC Parameter (AC operating conditions unless otherwise noted) Symbol Parameter t Row active to row active delay RRD(min) t RCD(min) RAS to CAS delay t Row precharge time RP(min) t RAS(min) Row active time t RAS(max) t Row cycle ...
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Simplified Truth Table Command Register Mode Register Set Special Mode Register Set Refresh Auto Refresh Entry Self Refresh Exit Bank Active Write Per Bite Disable & Row Addr. Write Per Bit Enable Read & Auto Precharge Disable Column Addr. Auto ...
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PRELIMINARY (December, 1998, Version 0.0) A45L9332 Series AMIC Technology, Inc. 11 ...
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Mode Register Filed Table to Program Modes Register Programmed with MRS Address A10 A9 Function RFU W.B.L (Note 1) (Note 2) Test Mode A8 A7 Type 0 0 Mode Register Set 0 1 Vendor Use 1 0 Only 1 1 ...
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Burst Sequence (Burst Length = 4) Initial address Burst Sequence (Burst Length = 8) Initial address ...
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Device Operations Clock (CLK) The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation ...
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Device Operations (continued) Bank Activate The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read ...
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Device Operations (continued) or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t (max). Therefore, each bank RAS has to be precharged within t (max) from ...
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Device Operations (continued) attended not to induce bus contention. The more detailed materials can obtained by referring corresponding timing diagram. Write Per Bit Write per bit (i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of ...
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Summary of 2M Byte SGRAM Basic Features and Benefits Features 256K SGRAM Interface Synchronous Bank Page Depth / 1 Row Total Page Depth Burst Length (Read) 1,2,4,8 Full Page 1,2,4,8 Full Page Burst Length (Write) Burst ...
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DQM Operation 1) Write Mask (BL=4) CLK CMD WR DQMi Masked by CKE DQ(CL2 DQ(CL3 DQM to Data-in Mask = 0CLK 2) Read Mask (BL=4) CLK RD CMD CKE DQM Q0 DQ(CL2) DQ(CL3) ...
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CAS Interrupt (I) 1) Read intreupted by Read (BL=4) CKL CMD RD RD ADD A B DQ(CL2) QA0 DQ(CL3) t CCD Note2 2) Write interrupted by (Block) Write (BL =2) CKL WR WR CMD t CCD Note2 ADD A ...
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CAS Interrupt (II) : Read Interrupted Write & DQM (1) CL=2, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ iv) CMD RD DQM DQ (2) CL=3, BL=4 CLK i) CMD ...
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Write Interrupted by Precharge & DQM CLK CMD WR DQM Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise ...
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Burst Stop & Precharge Interrupt 1) Write Interrupted by Precharge (BL=4) CLK CMD WR DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS & SMRS 2) Mode Register Set CLK Note ...
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Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh Note 3 1) Auto Refresh CLK Note 4 CKE PRE Internal CLK ...
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About Burst Type Control Sequential counting Basic MODE Interleave counting Pseudo- Decrement Sequential Counting Pseudo- MODE Pseudo-Binary Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 ...
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Mask Functions 1) Normal Write I/O masking : By Mask at Write per Bit Mode, the selected bit planes keep the original data. If bit plane 0,3,7,9,15,22,24, and 31 keep the original value. i) STEP SMRS (LMR) : Load ...
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Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING ...
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Power On Sequence & Auto Refresh CLOCK CKE High level is necessary RAS CAS ADDR DSF DQM High level is necessary High-Z DQ Precharge Auto ...
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Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length CLOCK CKE *Note RCD t SH RAS CAS ...
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Note : 1. All inputs can be don’ t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by A10. A10 Enable and disable auto precharge function ...
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Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS t RCD RAS CAS ADDR Ra Ca0 A10 DSF DQM DQ ( RAC t *Note 3 SAC ...
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Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS t RCD RAS CAS ADDR Ra Ca0 A10 DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read (A-Bank) (A-Bank) ...
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Block Write Cycle (with Auto Precharge CLOCK CKE CS RAS CAS *Note 2 ADDR RAa CAa CAb A10 RAa A9 WE DSF t BWC DQM *Note 1 Pixel Pixel DQ Mask Mask Masked Row Active ...
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SMRS and Block/Normal Write @ Burst Length CLOCK CKE CS RAS CAS RAa A0-2 RAa CAa A3,4,7,8 A5 RAa CAa RAa CAa A6 A9 RAa A10 WE DSF DQM I/O Pixel DQ Color Mask Mask ...
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Page Read Cycle at Different Bank @Burst Length = CLOCK CKE *Note 1 CS RAS CAS RAa CAa RBb ADDR A10 RAa RBb A9 WE DSF DQM DQ (CL=2) DQ (CL=3) Row Active Row ...
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Page Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa Key CAa RBb ADDR A10 A9 RAa RBb WE DSF DQM Mask DAa0 DAa1 DAa2 DAa3 DQ Row Active Load Mask ...
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Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa CAa ADDR A10 A9 RAa WE DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read (A-Bank) (A-Bank) * Note : ...
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Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS RAa RBb CAa ADDR A10 RAa RBb A9 WE DSF DQMi DQ (CL=2) DQ (CL=3) Row Active Read with (A-Bank) ...
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Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR A10 DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read with (A-Bank) ...
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Read & Write Cycle with Auto Precharge III @Burst Length CLOCK CKE CS RAS CAS Ra Ca ADDR A10 DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read with (A-Bank) Auto Preharge ...
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Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full Page Only CLOCK CKE CS RAS CAS RAa CAa ADDR A10 * Note 1 A9 RAa WE DSF DQM DQ (CL=2) DQ (CL=3) Read ...
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Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only CLOCK CKE CS RAS CAS RAa CAa ADDR A10 * Note 1 A9 RAa WE DSF DQM DQ DAa0 DAa1 DAa2 ...
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Burst Read Single Bit Write Cycle @Burst Length=2, BRSW CLOCK CKE CS RAS CAS RAa CAa RBb ADDR A10 RBb A9 RAa WE DSF DQM DQ DAa0 (CL=2) DQ DAa0 (CL=3) Row Active Row Active ...
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Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length CLOCK CKE CS RAS CAS Ra Ca ADDR A10 DSF DQM Qa0 DQ Clock Row Active Read Suspension * Note ...
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Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length CLOCK t SS CKE * Note 1 *Note 3 CS RAS CAS ADDR A10 A9 WE DSF DQM DQ Precharge Power-down Entry * Note : 1. All ...
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Self Refresh Entry & Exit Cycle CLOCK * Note 2 CKE * Note RAS * Note 7 CAS ADDR A10 A9 WE DSF DQM DQ Hi-Z Self Refresh Entry * Note ...
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Mode Register Set Cycle CLOCK CKE High *Note 2 CS RAS * Note 1 CAS * Note 3 Key Ra ADDR WE DSF DQM DQ Hi-Z MRS New Command * Both banks precharge should be ...
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Function Truth Table (Table 1) Current CS RAS CAS WE State IDLE ...
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Function Truth Table (Table 1, Continued) Current CS RAS CAS WE State Write ...
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Function Truth Table (Table 1, Continued) Current CS RAS CAS WE State Block Write Recovering ...
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Function Truth Table for CKE (Table 2) Current CKE CKE CS State n Self Refresh ...
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... Ordering Information Part No. Cycle Time (ns) A45L9332F-7 7 A45L9332E-7 7 A45L9332F-8 8 A45L9332E-8 8 A45L9332F-10 10 A45L9332E- QFP (Height = 3.0mm Max) LQFP (Height = 1.4mm Max) PRELIMINARY (December, 1998, Version 0.0) Clock Frequency (MHz) Access Time 143 6 143 6 125 6 125 6 100 7 100 7 ...
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Package Information QFP 100L Outline Dimensions 81 100 Symbol Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b ...
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Package Information LQFP 100L Outline Dimensions 81 100 Symbol H H Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material ...