CD54HC73F

Manufacturer Part NumberCD54HC73F
DescriptionHigh Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125
ManufacturerTexas Instruments
CD54HC73F datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
Page 1/15

Download datasheet (445Kb)Embed
Next
Data sheet acquired from Harris Semiconductor
SCHS134E
February 1998 - Revised September 2003
Features
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical f
= 60MHz at V
= 5V, C
MAX
CC
o
T
= 25
C
A
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Pinout
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
Description
The ’HC73 and CD74HCT73 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
= 15pF,
L
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
o
o
C to 125
C
Ordering Information
PART NUMBER
CD54HC73F3A
CD74HC73E
= 30% of V
IH
CC
CD74HC73M
CD74HC73MT
CD74HC73M96
CD74HCT73E
CD74HCT73M
1 A at V
, V
OL
OH
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CD54HC73 (CERDIP)
CD74HC73, CD74HCT73 (PDIP, SOIC)
TOP VIEW
1CP
1
14
1J
1R
2
13
1Q
1K
3
12
1Q
V
4
11
GND
CC
2CP
5
10
2K
2R
6
9
2Q
2J
7
8
2Q
1
CD54HC73, CD74HC73,
CD74HCT73
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC

CD54HC73F Summary of contents

  • Page 1

    ... HC/HCT107 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS logic family 125 C Ordering Information PART NUMBER CD54HC73F3A CD74HC73E = 30 CD74HC73M CD74HC73MT CD74HC73M96 CD74HCT73E CD74HCT73M ...

  • Page 2

    CD54HC73, CD74HC73, CD74HCT73 Functional Diagram =High Level (Steady State) L =Low Level (Steady State Irrelevant = High-to-Low Transition Logic Diagram ...

  • Page 3

    CD54HC73, CD74HC73, CD74HCT73 Absolute Maximum Ratings DC Supply Voltage -0. Input ...

  • Page 4

    CD54HC73, CD74HC73, CD74HCT73 DC Electrical Specifications (Continued) CONDITIONS PARAMETER SYMBOL V (V) I Quiescent Device Current GND HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output ...

  • Page 5

    CD54HC73, CD74HC73, CD74HCT73 Prerequisite For Switching Specifications PARAMETER SYMBOL Setup Time Hold Time Removal Time t REM CP Frequency f MAX HCT TYPES CP Pulse Width t w ...

  • Page 6

    CD54HC73, CD74HC73, CD74HCT73 Switching Specifications Input PARAMETER SYMBOL Input Capacitance C I Power Dissipation Capacitance C PD (Notes 3, 4) HCT TYPES Propagation Delay PLH PHL Propagation Delay ...

  • Page 7

    CD54HC73, CD74HC73, CD74HCT73 Test Circuits and Waveforms 90% CLOCK INPUT 10% t H(H) DATA INPUT t SU(H) t TLH 90% OUTPUT t PLH t REM V CC SET, RESET 50% OR PRESET ...

  • Page 8

    ... PACKAGING INFORMATION (1) Orderable Device Status 5962-8515301CA ACTIVE CD54HC73F ACTIVE CD54HC73F3A ACTIVE CD74HC73E ACTIVE CD74HC73EE4 ACTIVE CD74HC73M ACTIVE CD74HC73M96 ACTIVE CD74HC73M96E4 ACTIVE CD74HC73M96G4 ACTIVE CD74HC73ME4 ACTIVE CD74HC73MG4 ACTIVE CD74HC73MT ACTIVE CD74HC73MTE4 ACTIVE CD74HC73MTG4 ACTIVE CD74HCT73E ACTIVE CD74HCT73EE4 ACTIVE CD74HCT73M ACTIVE ...

  • Page 9

    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants ( not exceed 0.1% by weight in homogeneous ...

  • Page 10

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CD74HC73M96 SOIC D PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 14 2500 330.0 16.4 6.5 Pack Materials-Page 1 11-Mar-2008 ...

  • Page 11

    Device Package Type CD74HC73M96 SOIC PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2500 Pack Materials-Page 2 11-Mar-2008 Width (mm) Height (mm) 346.0 346.0 33.0 ...

  • Page 12

    ...

  • Page 13

    ...

  • Page 14

    ...

  • Page 15

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...