CD54HCT193F3A

Manufacturer Part NumberCD54HCT193F3A
DescriptionHigh Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters 16-CDIP -55 to 125
ManufacturerTexas Instruments
CD54HCT193F3A datasheet
 


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Data sheet acquired from Harris Semiconductor
SCHS163F
September 1997 - Revised October 2003
Features
• Synchronous Counting and Asynchronous
Loading
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, N
IL
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), V
= 2V (Min)
IL
IH
- CMOS Input Compatibility, I
l
Description
The ’HC192, ’HC193 and ’HCT193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Pinout
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)
CD74HC192 (PDIP, SOP, TSSOP)
CD74HC193 (PDIP, SOIC)
CD74HCT193 (PDIP)
TOP VIEW
P1
1
Q1
2
Q0
3
CPD
4
CPU
5
Q2
6
Q3
7
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
©
Copyright
2003, Texas Instruments Incorporated
CD54/74HC193, CD54/74HCT193
Presettable Synchronous 4-Bit Up/Down Counters
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
o
o
low half a clock period before the maximum count (9 in the
C to 125
C
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and Clock-Down inputs, respectively, of the next most
significant counter.
If a decade counter is preset to an illegal state or assumes an
= 30% of V
illegal state when power is applied, it will return to the normal
IH
CC
sequence in one count as shown in state diagram.
Ordering Information
PART NUMBER
1 A at V
, V
OL
OH
CD54HC192F3A
CD54HC193F3A
CD54HCT193F3A
CD74HC192E
CD74HC192NSR
CD74HC192PW
CD74HC192PWR
CD74HC192PWT
CD74HC193E
CD74HC193M
16
V
CC
CD74HC193MT
15
P0
CD74HC193M96
14
MR
CD74HCT193E
13
TCD
12
TCU
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
11
PL
reel of 250.
10
P2
9
P3
1
CD54/74HC192,
High-Speed CMOS Logic
TEMP. RANGE
o
(
C)
PACKAGE
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld CERDIP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld TSSOP
-55 to 125
16 Ld PDIP
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld SOIC
-55 to 125
16 Ld PDIP

CD54HCT193F3A Summary of contents

  • Page 1

    ... If a decade counter is preset to an illegal state or assumes illegal state when power is applied, it will return to the normal IH CC sequence in one count as shown in state diagram. Ordering Information PART NUMBER CD54HC192F3A CD54HC193F3A CD54HCT193F3A CD74HC192E CD74HC192NSR CD74HC192PW CD74HC192PWR CD74HC192PWT CD74HC193E CD74HC193M CD74HC193MT 15 P0 ...

  • Page 2

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Functional Diagram ASYN. PARALLEL LOAD ENABLE CLOCK DOWN CLOCK High Voltage Level Low Voltage Level Don’t Care, High Level BCD/BINARY PRESET ...

  • Page 3

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Absolute Maximum Ratings DC Supply Voltage -0. Input ...

  • Page 4

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 DC Electrical Specifications (Continued) PARAMETER SYMBOL V (V) I HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage V IL CMOS Loads ...

  • Page 5

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL HC TYPES Pulse Width t W CPU, CPD 192 t W CPU, CPD 193 Set-up Time Hold Time t H ...

  • Page 6

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL Set-up Time Hold Time Hold Time t H CPD to CPU or CPU to CPD ...

  • Page 7

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Switching Specifications Input PARAMETER SYMBOL CPD PLH PLH Transition Time t TLH Q, TCU, TCD Input Capacitance Power Dissipation Capacitance ...

  • Page 8

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms MASTER RESET ASYNCHRONOUS PARALLEL LOAD PRESET DATA SEQUENCES: 1. RESET OUTPUTS TO ZERO. CLOCK UP 2. LOAD (PRESET) TO BCD SEVEN. 3. COUNT UP TO EIGHT, NINE, CLOCK DOWN TERMINAL COUNT UP, ZERO, ...

  • Page 9

    CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms MASTER RESET ASYNCHRONOUS PARALLEL LOAD PRESET DATA SEQUENCES: 1. RESET OUTPUTS TO ZERO. 2. LOAD (PRESET) TO BINARY THIRTEEN. 3. COUNT UP TO FOURTEEN, FIFTEEN, TERMINAL COUNT UP, CLOCK DOWN ZERO, ONE AND ...

  • Page 10

    Test Circuits and Waveforms FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL) UP CLOCK DOWN CLOCK ASYNCHRONOUS, PARALLEL LOAD RESET FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD ...

  • Page 11

    ... PACKAGING INFORMATION (1) Orderable Device Status 5962-8780801EA ACTIVE 5962-9084801MEA ACTIVE 9084801MEAS2035 OBSOLETE CD54HC192F3A ACTIVE CD54HC193F3A ACTIVE CD54HCT193F3A ACTIVE CD74HC192E ACTIVE CD74HC192EE4 ACTIVE CD74HC192NSR ACTIVE CD74HC192NSRE4 ACTIVE CD74HC192NSRG4 ACTIVE CD74HC192PWR ACTIVE CD74HC192PWRE4 ACTIVE CD74HC192PWRG4 ACTIVE CD74HC192PWT ACTIVE CD74HC192PWTE4 ACTIVE CD74HC192PWTG4 ACTIVE ...

  • Page 12

    Orderable Device Status CD74HC193MTG4 ACTIVE CD74HCT193E ACTIVE CD74HCT193EE4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy ...

  • Page 13

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CD74HC192NSR SO NS CD74HC192PWR TSSOP PW CD74HC193M96 SOIC D PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 16 2000 330.0 ...

  • Page 14

    Device Package Type CD74HC192NSR SO CD74HC192PWR TSSOP CD74HC193M96 SOIC PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 PW 16 2000 D 16 2500 Pack Materials-Page 2 19-Mar-2008 Width (mm) Height (mm) ...

  • Page 15

    PW (R-PDSO-G**) 14 PINS SHOWN 0, 0,15 1,20 MAX 0,05 PINS ** DIM A MAX A MIN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body ...

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  • Page 21

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...