CD54HCT373F3A

Manufacturer Part NumberCD54HCT373F3A
DescriptionHigh Speed CMOS Logic Octal Transparent Latches with 3-State Output 20-CDIP -55 to 125
ManufacturerTexas Instruments
CD54HCT373F3A datasheet
 


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4.5-V to 5.5-V V
Operation
CC
Wide Operating Temperature Range of
–55 C to 125 C
Balanced Propagation Delays and
Transition Times
Standard Outputs Drive Up To 10 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible
description/ordering information
The ’HCT373 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
T A
PDIP – E
–55 C to 125 C
55 C to 125 C
SOIC
SOIC – M
CDIP – F
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OCTAL TRANSPARENT D-TYPE LATCHES
SCLS453B – FEBRUARY 2001 – REVISED MAY 2003
CD54HCT373 . . . F PACKAGE
CD74HCT373 . . . E OR M PACKAGE
GND
ORDERING INFORMATION
ORDERABLE
PACKAGE †
PART NUMBER
Tube
CD74HCT373E
Tube
CD74HCT373M
M
Tape and reel
CD74HCT373M96
Tube
CD54HCT373F3A
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CD54HCT373, CD74HCT373
WITH 3-STATE OUTPUTS
(TOP VIEW)
OE
V
1
20
CC
1Q
8Q
2
19
1D
8D
3
18
2D
7D
4
17
2Q
7Q
5
16
3Q
6Q
6
15
3D
6D
7
14
4D
8
13
5D
4Q
9
12
5Q
10
11
LE
through a pullup
CC
TOP-SIDE
MARKING
CD74HCT373E
HCT373M
HCT373M
CD54HCT373F3A
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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CD54HCT373F3A Summary of contents

  • Page 1

    ... LE through a pullup CC TOP-SIDE MARKING CD74HCT373E HCT373M HCT373M CD54HCT373F3A Copyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. 1 ...

  • Page 2

    CD54HCT373, CD74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS453B – FEBRUARY 2001 – REVISED MAY 2003 logic diagram (positive logic absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage ...

  • Page 3

    Note Supply voltage V IH High-level input voltage V IL Low-level input voltage V I Input voltage V O Output voltage t/ v Input transition rise or fall rate NOTE 3: All unused ...

  • Page 4

    CD54HCT373, CD74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS453B – FEBRUARY 2001 – REVISED MAY 2003 timing requirements over recommended operating free-air temperature range, V otherwise noted) (see Figure Pulse duration, LE high t su Setup ...

  • Page 5

    PARAMETER MEASUREMENT INFORMATION Test 1 k Point From Output Under Test C L (see Note A) LOAD CIRCUIT CLR 1.3 V Input CLK VOLTAGE WAVEFORMS RECOVERY TIME Input 1 PLH In-Phase 90% 1.3 V Output 10 ...

  • Page 6

    ... PACKAGING INFORMATION (1) Orderable Device Status CD54HCT373F ACTIVE CD54HCT373F3A ACTIVE CD74HCT373E ACTIVE CD74HCT373EE4 ACTIVE CD74HCT373M ACTIVE CD74HCT373M96 ACTIVE CD74HCT373M96G4 ACTIVE CD74HCT373MG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

  • Page 7

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CD74HCT373M96 SOIC DW PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 20 2000 330.0 24.4 10.8 Pack Materials-Page 1 11-Mar-2008 ...

  • Page 8

    Device Package Type CD74HCT373M96 SOIC PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 Pack Materials-Page 2 11-Mar-2008 Width (mm) Height (mm) 346.0 346.0 41.0 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...