STE400P STMicroelectronics, STE400P Datasheet

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STE400P

Manufacturer Part Number
STE400P
Description
STE400P - 4 PORT 10-100 FAST ETHERNET TRANSCEIVER - PHY DATASHEET
Manufacturer
STMicroelectronics
Datasheet
1.0 024DESCRIPTION
The STE400P, also referred to as STEPHY4, is a
high performance Fast Ethernet physical layer inter-
face for 10BASE-T and 100BASE-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100BASE-
TX of IEEE802.3u and 10BASE-T of IEEE802.3.
The STE400P supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2.0 FEATURE
2.1 Industry standard
Figure 1. BLOCK DIAGRAM FOR 1 PORT
September 2001
REVISION: A09
This is preliminary information on a product now in development. Details are subject to change without notice.
• IEEE802.3u 100BASE-TX and IEEE802.3
HW
configuration
pins
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
10BASE-T compliant
LEDS
RXD[3:0]
RX_ER
RX_DV
RX_CLK
COL
CRS
HW Config
Power Down
LEDS
10/100 FAST ETHERNET 4 PORT TRANSCEIVER
100Mb/s
100Mb/s
10Mb/s
4B/5B
4B/5B
10Mb/s
Descrambler
Code Align
NRZ To Manchester
Encoder
Scrambler
NRZ To Manchester
Encoder
REGISTERS
TX Channel
Serial to
Parallel
RX Channel
Parallel to
Serial
Link Pulse
Detector
NRZI To NRZ
Decoder
NRZ To NRZI
Encoder
Link Pulse
Generator
Auto
Negotiation
• Support for IEEE802.3x flow control
• IEEE802.3u Auto-Negotiation support for
• MII interface
• Standard CSMA/CD or full duplex operation
10BASE-T and 100BASE-TX
supported
Binary To MLT3
Decoder
Clock Recovery
10 TX Filter
Clock Recovery
ORDERING NUMBER: STE400P
Binary To MLT3
Encoder
Loopback
10 TX
Filter
PQFP208
Adaptive
Equalization
BaseLine
Wander
SMART
Squelch
STE400P
TRANSMITTER
10/100
Clock
Generation
RECEIVER
10/100
TXP
TXN
RXP
RXN
System
Clock
1/34

Related parts for STE400P

STE400P Summary of contents

Page 1

... FAST ETHERNET 4 PORT TRANSCEIVER 1.0 024DESCRIPTION The STE400P, also referred to as STEPHY4 high performance Fast Ethernet physical layer inter- face for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100BASE IEEE802 ...

Page 2

... Second mode – 4 LED displays for 100 Link(On when 100M link or 10 Link(On when 10M link ok • Activity (Blink with 10Hz when receiving or transmitting) • FD(Keeps on when in Full duplex mode) or Collision(Blink with 20Hz when colliding) 3.0 SYSTEM DIAGRAM OF THE STE400P APPLICATION QUAD ETHERNET MAC CONTROLLER 4 PORT 10/100MBPS PHY ...

Page 3

... PIN ASSIGNMENT DIAGRAM STE400P 3/34 ...

Page 4

... Receive Data. The STE400P drives received data on these outputs, synchronous to RX-CLK. RXD4 is driven only in Symbol (5B) Mode. Receive Data Valid. The STE400P asserts This signal when it drives valid data on RXD. This output is synchronous to RX-CLK. Receive Error. The STE400P asserts this output when it receives invalid symbols from the network ...

Page 5

... Maximum frequency is 2.5 MHz. Management Data Input/Output, Bi-directional serial data channel for PHY communication. Reset: Active low. Resets the STE400P. Pin not included in NAND Reference clock input MHz This pin must be driven with a continuous 25 MHz clock. Transmit Pair: Differential data is transmitted to the media on the TD+- ...

Page 6

... STE400P Table 1. Pin Description Pin. Name Type 204 SP100LED# {1} O 185 SP100LED# {2} 177 SP100LED# {3} 158 SP100LED# {4} XMTLED#{1} 202 INTR# {1} FDXLED# {1} XMTLED#{2} 183 INTR# {2} FDXLED# {2} Ood Ser SDO# XMTLED#{3} 179 INTR# {3} FDXLED# {3} XMTLED#{4} 160 INTR# {4} FDXLED# {4} RCVLED#{1} 201 ACTLED {1} LC Ser SCLK# ...

Page 7

... DVDD or left floating Input VDD: +5.0V or +3.3V. If any of the inputs are driven to 5.0V, this pin must be connected to the 5.0V supply. If none of the inputs are driven above 3.3V, this pin may be connected to the 3.3V supply Phase Locked Loop VDD Phase Locked Loop GND Bias VDD STE400P 7/34 ...

Page 8

... STE400P Table 1. Pin Description Pin. Name Type 80 BIASGND 63 72 AVDD AGND 175 DVDD 198 176 DGND 197 13 129 144 OVDD 162 173 200 107 128 OGND 135 143 154 163 174 188 ...

Page 9

... Because of this, the COL pin will normally not be activated during loopback mode. In order to test that the COL pin is actually working, the STE400P may be placed into collision test mode. This mode is enabled by writing a “1” to bit 7 of the MII Control Register. Asserting TXEN will cause the COL output to go high and deas- serting TXEn will cause the COL output to go low. The loopback mode may be entered by writing a “ ...

Page 10

... STE400P 7.0 REGISTERS AND DESCRIPTORS DESCRIPTION There are 20 registers with 16 bits each supported for each port of the STE400P. This includes 9 basic registers which are defined according to the clause 22 “Reconciliation Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of IEEE802 ...

Page 11

... Table 3. Register Descriptions Bit # Name PR0, MII Control Register. The default values on power-up/reset are as listed below. 15 XRST Reset control. 1: Device will be reset. This bit will be cleared by STE400P itself after the reset is completed. 14 XLBEN Loop-back mode select. 1: Loop-back mode is selected. 13 SPSEL Network Speed select. This bit’ ...

Page 12

... T4 100BASE-T4 ability. Always 0, since STE400P has no T4 ability. 14 TXFD 100BASE-TX full duplex ability. Always 1, since STE400P has the 100BASE-TX full duplex ability. 13 TXHD 100BASE-TX half duplex ability. Always 1, since STE400P has the 100BASE-TX half duplex ability. 12 10FD 10BASE-T full duplex ability. ...

Page 13

... LPACK Received Link Partner Acknowledge. 0: link code work had not received yet. 1: link partner successfully received STE400P’s Link Code Word. 13 LPRF Link Partner’s Remote fault status remote fault detected. 1: remote fault detected. ...

Page 14

... LPNP Link Partner’s Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability STE400P’s next Page ability. 0: without next page ability. 1: with next page ability Page Received new page has been received. ...

Page 15

... NRZ and NRZI. 0: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting. 7~0 --- Reserved. Ignore on Read PR10- 100 AUX SR, 100BaseX Auxiliary Status Register 15~10 --- Reserved 9 Locked 1: descrambler locked 0: descrambler unlocked Descriptions STE400P Default Val RW Type ...

Page 16

... STE400P Table 3. Register Descriptions Bit # Name 8 100 LS Current 100BaseX link status 1: link pass 0: link fail 7~6 Reserved 5 FCD 1: False Carrier Detected since last read 0: no False Carrier since last read 4 BAD ESD 1: ESD error detected since last read 0: no ESD error since last read ...

Page 17

... ANFLGC 1=Auto Negotiation FLP-Link Good Check 13 ANAD 1=Auto Negotiation acknowledge detected 12 ANABD 1=Auto Negotiation for link partner ability 11 ANP STE400P and link partner Pause Operation bit set 10~8 AN HCD 000=NO Highest Common Denominator 001=10Base-T 010=10Base-T Full-duplex 011=100Base-TX 100=100Base-T4 101=100Base-TX Full-duplex 11x= undefined ...

Page 18

... STE400P Table 3. Register Descriptions Bit # Name 14 INTR E Interrupt Enable 13 Reserved 12 NP Mask Next-Page Interrupt Mask 11 FDX Mask Full-duplex Interrupt Mask 10 SPD Mask SPEED Interrupt Mask 9 LK Mask Link Interrupt Mask 8 INTR Mask Master Interrupt Mask 7~5 Reserved 4 NP_LP Link-partner’s next-page received ...

Page 19

... Block TXEN mode 0 Reserved PR19- AUX MPR, Auxiliary Multiple PHY Register 15 HCD_TX_ 1=Auto Negotiation result is 100Base-TX full-duplex FDX 14 HCD_T4 0=STE400P doesn’t support 100Base-T4 ability 13 HCD_TX 1=Auto Negotiation result is 100Base-TX 12 HCD_FDX 1=Auto Negotiation result is 10Base-T full-duplex (10Base-T) 11 HCD 1=Auto Negotiation result is 10Base-T ...

Page 20

... RXER Code Mode SC = Self Clear 8.0 DEVICE OPERATION The STE400P integrates the IEEE802.3u compliant functions of PCS(physical coding sub-layer), PMA(physical medium attachment) sub-layer, and PMD(physical medium dependent) sub-layer for 100BASE-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the func- tions and operation schemes are described in the following sections ...

Page 21

... PR0 register to 1 can enable the loop-back option. In this loop-back operation, the TX± and RX± lines are isolated from the media. The STE400P also provides remote loop-back operation for 100BASE-TX opera- tion. Setting bit 9 of PR19 register to 1 enables the remote loop-back operation. ...

Page 22

... The active low Reset input signal is required at least ensure proper reset operation. Second, for software reset, when bit 15 of register PR0 is set to 1, the STE400P will reset entire circuits and registers to their default values, and clear the bit 15 of PR0 to 0. Both hardware and software reset operations initialize all registers to their default values ...

Page 23

... Logic Level 1 8.11 Preamble Suppression Preamble suppression mode in the STE400P is indicated by a one in bit six of the PR1 Register deter- mined that all PHY devices in the system support preamble suppression, then a preamble is not necessary for each management transaction. The first transaction following power-up/hardware reset requires 32 bits of pre- amble ...

Page 24

... STE400P 9.0 ELECTRICAL SPECIFICATIONS AND TIMINGS Table 4. Absolute Maximum Ratings Parameter Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection Table 5. General DC Specifications Symbol Parameter General DC Vcc Supply Voltage 10BASE-T Voltage/Current Characteristics Vida10 Input Differential Accept Peak Voltage Vidr10 ...

Page 25

... FLP Width Tflcpp Clock pulse to clock pulse period Tflcpd Clock pulse to Data pulse period - Number of pulses in one burst Tflbw Burst Width Tflbp FLP Burst period Test Condition 10Mbps 10Mbps Test Condition STE400P Min. Typ. Max. Units PPM 100 Min ...

Page 26

... STE400P Figure 3. Fast Link Pulse timing Tflbw Table 7. AC Specifications Symbol Parameter 100BASE-TX Transmitter AC Timings Specification Tjit TDP-TDN Differential Output Peak Jitter MII Management Clock Timing Specifications t1 MDC Low Pulse Width t2 MDC High Pulse Width t3 MDC Period t4 MDIO(I) Setup to MDC Rising ...

Page 27

... RX-CLK High Pulse Width (100 Mbits/s) RX-CLK High Pulse Width (10 Mbits/s) t4 RX-CLK Low Pulse Width (100 Mbits/s) RX-CLK Low Pulse Width (10 Mbits/s) t5 RX-CLK Period (100 Mbits/s) RX-CLK Period (10 Mbits/ Test Condition STE400P t3 Min. Typ. Max. Units 10 — — 200 ns 14 ...

Page 28

... STE400P Figure 5. MII Receive Timing Table 7. AC Specifications Symbol Parameter MII Transmit Timing Specification t1 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise t2 TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise Figure 6. MII Transmit Timing 28/34 Test Condition Min Typ. Max. Units — ...

Page 29

... Edge of RX-DV (10 Mbits/s) Rt4 End of Receive Frame to CRS Low (100 Mbits/s) End of Receive Frame to CRS Low (10 Mbits/s) Figure 7. Receive Timing Test Condition Min. — — — — — — 13 — STE400P Typ. Max. Units 15 bits 22 bits 13 Bits 5 bits 12 bits 4 bits 24 bits 4 ...

Page 30

... STE400P Table 7. AC Specifications Symbol Parameter Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) t3 Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) t4 Sampled TX-EN Inactive to End of Frame (100 Mbits/s) Sampled TX-EN Inactive to End ...

Page 31

... TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. Sym Min Typ Max t2A t2B t2C - 3 4 t2D - 4 16 t2E STE400P Units 31/34 ...

Page 32

... STE400P Figure 12: 10Base-T Transmit Timing TXP Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. ...

Page 33

... STE400P 9.0 PACKAGE 33/34 ...

Page 34

... STE400P PACKAGE TYPE: PQFP 208 / BODY 28X28X3.49mm REF MIN. A 0.25 A1 3.40 A2 0. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics ...

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