PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 67

• Manufacturer Part Number: PM5361-RI
• Description: SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
• Manufacturer: PMC-Sierra, Inc.

DATA SHEET
PMC-920526
LOPE:
LOPV:
PF:
CONFIG[1:0]:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
inverted, causing downstream pointer processing elements to enter a loss of
pointer state. Insertion of an inverted new data flag can occur in concert with
the insertion of a normal idle (unequipped) indication as directed by the IIDLE
bit. The DLOP bit has no effect when the IPAIS bit is set high.
The LOPE bit enables loss of pointer interrupts for tributary TU #3 in the
corresponding TUG2. When LOPE is set high, an interrupt is generated upon
loss of pointer and upon re-acquisition. Interrupts due to LOP status change
are masked when LOPE is set low.
The LOPV bit indicates the loss of pointer status of tributary TU #3 in the
corresponding TUG2.
The PF bit enables pointer follower mode for tributary TU #3 in the
corresponding TUG2. In pointer follower mode, the tributary FIFO dead-zone
is collapsed so that any variation is FIFO depth will result in an outgoing
pointer justification event. Any TU pointer justification event on the
corresponding incoming tributary, or an AU pointer justification event affecting
this tributary will cause an outgoing pointer justification event.
The CONFIG[1:0] bits are read-only and reflect the values written into the
corresponding register of TU #1. The configuration specified by the
CONFIG[1:0] bits are selected as follows:
CONFIG[1]
0
0
1
1
CONFIG[0]
0
1
0
1
ISSUE 8
Configuration
TU2 (VT6)
VT3
TU12 (VT2)
TU11 (VT1.5)
Active TU (VT)
#1
#1, #2
#1, #2, #3
#1, #2, #3, #4
TRIBUTARY UNIT PAYLOAD PROCESSOR
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PM5361 TUPP