PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 75
PM5361-RI
Manufacturer Part Number
PM5361-RI
Description
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5361-RI.pdf
(108 pages)
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DATA SHEET
PMC-920526
11.1 I/O Test Mode
PMCTST:
In I/O test mode, the TUPP allows the logic levels on the device inputs to be read
through the microprocessor interface, and allows the device outputs to be forced
to either logic level through the microprocessor interface.
To enable I/O test mode, the IOTST bit in the Master Test register is set to
logic 1.
Reading the following address locations returns the values for the indicated
inputs :
Table 2
Writing the following address locations forces the outputs to the value in the
corresponding bit position:
Table 3
Addr
H82
H83
H84
Addr
H81
H82
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The PMCTST bit is used to configure the TUPP for PMC's manufacturing
tests. When PMCTST is set to logic 1, the TUPP microprocessor port
becomes the test access port used to run the PMC "canned" manufacturing
test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can
only be cleared by setting CSB to logic 1.
Bit 7
X
DIN7
X
Bit 7
DOUT7
0
- I/O Test Mode — Input Read Register Description
- I/O Test Mode — Output Write Register Description
Bit 6
X
DIN6
X
Bit 6
DOUT6
0
ISSUE 8
Bit 5
X
DIN5
X
Bit 5
DOUT5
0
Bit 4
X
DIN4
SCLK
Bit 4
DOUT4
0
X
DIN3
DOUT3
INTB
Bit 3
ITMF
Bit 3
TRIBUTARY UNIT PAYLOAD PROCESSOR
Bit 2
OTMF
DIN2
ISPE
Bit 2
DOUT2
OTV5
Bit 1
OC1J1
DIN1
IC1J1
Bit 1
DOUT1
OTSPE
67
PM5361 TUPP
Bit 0
OSPE
DIN0
IPAR
Bit 0
DOUT0
OPAR
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