PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 96

• Manufacturer Part Number: PM5361-RI
• Description: SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
• Manufacturer: PMC-Sierra, Inc.

DATA SHEET
PMC-920526
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
2. Maximum output propagation delays are measured with a 100 pF load on the
3. a. In Intel mode, a valid read enable bar is defined as a logical OR of the CSB
4. Microprocessor Interface timing applies to normal mode register accesses
5. In non-multiplexed address/data bus architectures, ALE should be held high,
6. Parameters tH
7. When a set-up time is specified between an input and a clock, the set-up time
8. When a hold time is specified between an input and a clock, the hold time is
Table 6
Symbol
tS
tS
tS
tH
tV
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
AW
DW
ALW
L
ALW
point of the reference signal to the 1.4 Volt point of the output.
Microprocessor Interface data bus, (D[7:0]).
and the RDB signals.
b. In Motorola mode, a valid read enable is defined as a logical AND of the E
signal, the RWB signal, and the inverted CSB signal.
only.
parameters tS
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
- Microprocessor Interface Write Access (Figure 19, Figure 20)
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
ALR
AR
and tS
, tH
ISSUE 8
ALR
AR
, tV
are not applicable if address latching is used.
L
, and tS
LR
are not applicable.
TRIBUTARY UNIT PAYLOAD PROCESSOR
20
Min
25
20
20
20
Max
88
PM5361 TUPP
Units
ns
ns
ns
ns
ns