PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 105

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

10.15.7 Data Scrambling
10.16 Transmit Scalable Data Queue (TXSDQ)
10.16.1 Transmit ATM FIFO
10.16.2 Transmit POS FIFO
10.17 Transmit Phy Interfaces (RXPHY and TXPHY)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
The Scrambler will optionally scramble the whole packet data, including the FCS and the flags.
Scrambling is performed after the POS frame is formed using a parallel implementation of the
self-synchronous scrambler polynomial, x 43 +1. On reset, the scrambler is set to all ones to
ensure scrambling on start-up. The scrambler may optionally be completely disabled. Data
scrambling can provide for a more robust system preventing the injection of hostile patterns into
the data stream.
The TXSDQ provides a FIFO to separate the line-side timing from the higher layer ATM/POS
link layer timing. The TXSDQ has two modes of operations, ATM and POS.
The TXSDQ is responsible for holding up to 48 cells until they can be read and transmitted. The
cells are written in with a single 32-bit data bus running off TFCLK and are read out at the
channel rate. Internal read and write pointers track the cells and indicate the fill status of the
Transmit FIFO. Separate read and write clock domains provide for separation of the physical
layer line timing from the System Link layer timing (TFCLK).
The TXSDQ contains 192 sixteen-byte blocks for FIFO storage, along with management circuitry
for reading and writing the FIFO. Octets are written in with a single 32-bit data bus running off
TFCLK and are read out with a single 32-bit data bus. Separate read and write clock domains
provide for separation of the physical layer line timing from the System Link layer timing.
Packets always begin at the beginning of a block and will not use up left-over space in a block
used by a previous packet.
Internal read and write pointers track the insertion and removal of octets, and indicate the fill
status of the Transmit FIFO. These status indications are used to detect underrun and overrun
conditions, abort packets as appropriate on both System and Line sides, control flag insertion and
to generate the DTPA output.
The S/UNI-2488 transmit system interface can be configured for ATM or POS mode. When
configured for ATM applications, the system interface provides a 32-bit transmit UTOPIA Level
3 compatible bus to allow the transfer of ATM cells between the ATM layer device and the
S/UNI-2488. When configured for POS applications, the system interface provides a 32-bit POS-
PHY Level 3 compliant bus for the transfer of ATM cells and data packets between the link layer
device and the S/UNI-2488. The link layer device can implement various protocols, including
PPP and HDLC.
7D (Control Escape)
Abort Sequence
7D-5D
7D-7E
S/UNI-2488 Telecom Standard Product Datasheet
Released
105