PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 131

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0002H: S/UNI-2488 Transmit Control Register
The reserved bit 0 must be set to logic one for normal operation of the S/UNI 2488.
RESYNC_EN
DIAGSHORT
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The RESYNC_EN bit is used to tie the transmit frame’s J0 position with the incoming
APSIFP. This is to ensure a deterministic latency through the device as required for
interfacing to another S/UNI-2488 or potentially a CHESS device via the APS ports. Initially,
the framing is arbitrary. If RESYNC_EN is logic ‘1’, then the S/UNI-2488 will compare the
internal frame pulse location to that of the APSIFP. If they ever differ by the number of clock
cycles specified in the APSIFP_THRESH[7:0] field in register 000EH, then the frame pulse
will snap to the position indicated by the APSIFP input. If RESYNC_EN is logic ‘0’, the
frame pulse will internally flywheel in its current alignment. Note that even if RESYNC_EN
is set low, it is still necessary to provide a proper APSIFP signal as the receive APS side is not
affected by the resynchronization logic. This register bit should always be set to logic 1 for
normal operation of the S/UNI-2488.
The diagnostic short frame (DIAGSHORT) bit sets a reduced frame size. This register bit is
for test purposes only.
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CXUCLKO_OEB
TREQ_ADVANCE[6]
TREQ_ADVANCE[5]
TREQ_ADVANCE[4]
TREQ_ADVANCE[3]
TREQ_ADVANCE[2]
TREQ_ADVANCE[1]
TREQ_ADVANCE[0]
SS_H1[1]
SS_H1[0]
SS_CONCAT[1]
SS_CONCAT[0]
TPAIS_EN
DIAGSHORT
RESYNC_EN
Reserved
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
1
1
0
0
1
1
0
0
1
0
0
0
0
0
1
1
Released
131