PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 133

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0003H: S/UNI-2488 Clock Monitors
TFCLKA
RFCLKA
RCLKA
TCLKA
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The TFCLK active (TFCLKA) bit monitors for low to high transitions on the TFCLK
transmit FIFO clock input. TFCLKA is set high on a rising edge of TFCLK, and is set low
when this register is read.
The RFCLK active (RFCLKA) bit monitors for low to high transitions on the RFCLK receive
FIFO clock input. RFCLKA is set high on a rising edge of RFCLK, and is set low when this
register is read.
The RCLK active (RCLKA) bit monitors for low to high transitions on the internal receive
system clock (RCLK). RCLKA is set high on a rising edge of RCLK, and is set low when
this register is read. This bit is not affected by RCLKEN (Register 0030H, bit 1).
The TCLK active (TCLKA) bit monitors for low to high transitions on the internal transmit
system clock (TCLK). TCLKA is set high on a rising edge of TCLK, and is set low when
this register is read. This bit is not affected by TCLKEN (Register 0038H, bit 1).
Type
R
R
R
R
R
Unused
Unused
Unused
Unused
Unused
Unused
APSIFPCLKA
RCLKA
TCLKA
RFCLKA
TFCLKA
Function
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
133