PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 136

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Document ID: PMC-2000489, Issue 4
Register 0005H: S/UNI-2488 Master Interrupt Status #2
This register allows the source of an active interrupt to be identified down to the block level.
Further register accesses are required for the block in question to determine the cause of an active
interrupt and to acknowledge the interrupt source.
RHPPI[2]… PRGMI[2]
INTE[2]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The RHPPI[2] to PRGMI[2] are interrupt status indicators for the corresponding block. The
interrupt status is set to logic 1 to indicate a pending interrupt from the corresponding block.
The interrupt status bits are independent of the interrupt enable bit.
The interrupt enable (INTE[2]) bit controls the assertion of the interrupt (INTB) output.
When a logic 1 is written to INTE[2], the RRMP[2]…PRGM[2] pending interrupt will assert
the interrupt (INTB) output. When a logic 0 is written to INTE[2], the RRMP[2]…PRGM[2]
pending interrupt will not assert the interrupt (INTB) output.
Type
R/W
R
R
R
R
INTE[2]
Unused
Unused
PRGMI[2]
Unused
Unused
SVCAI[2]
RHPPI[2]
Reserved
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
136

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