PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 152

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
LOS_I
FIFO_ERROR_I
PRBS_ERR_I
PRBS_SYNC_I
If the optical signal is lost, the SD input pin should be deasserted. This will cause the CRU
into training mode where it will lock onto the REFCLK input. However, the state-machine
which controls DOOL_I will continue to search for lock to data and is expected to toggle
during this time. When the optical signal is restored and the SD input pin is asserted, the
CRU will once again attempt to lock onto the data signal. Once lock is found, DOOL_I will
stop toggling and DOOLV can be examined to verify the CRU is in fact locked to the data.
The loss of signal status indicates that the receive signal is lost or that at least LOS_COUNT
consecutive ones or zeros have been received. LOS_I is a logic zero if the SDI input is high
or less than LOS_COUNT consecutive ones or zeros have been received. LOS_I is a logic
one if the SDI input is low or LOS_COUNT consecutive ones or zeros have been received.
Note: recall that LOS_COUNT is specified as the upper 5 bits of a 9 bit number and has an
accuracy of ±15. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The FIFO Error bit provides a status indication of an underflow or overflow condition in the
Rx data elastic store. When FIFO_ERROR_I is set to ‘1’, the data in the elastic store has been
corrupted and invalid data has been read from the FIFO. If WCIMODE in register 0001H is
set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then
a read of this register automatically clears the bit.
The PRBS Bit Error bit provides a status indication that a bit error has been detected in the
comparison between the incoming data and the locally generated data. The PRBS_ERR_I is
set high when the monitor is in the synchronized state and when an error in a PRBS word is
detected. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The PRBS Synchronization bit indicates that a change in the status of the PRBS Monitor has
occurred. The comparison between the incoming data and the internal PRBS^23 pattern is
generated locally. The PRBS_SYNC_I is set high when the monitor is in the synchronized
state and has received two consecutive erroneous words forcing the PRBS monitor to
resynchronize. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
S/UNI-2488 Telecom Standard Product Datasheet
Released
152