PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 155

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
FIFO_ERROR_EN
PRBS_ERR_EN
PRBS_SYNC_EN
SD_DISABLE
The FIFO Error Enable bit connects the FIFO_ERROR_I status bit to the INT pin of the
RCS_2488. When FIFO_ERROR_EN is set to logic one, an interrupt on the INT is
generated upon assertion of the FIFO_ERROR_I register bit. When FIFO_ERROR_EN is set
low, a change in the FIFO_ERROR_I status does not generate an interrupt.
The PRBS Error Enable bit connects the PRBS_ERR_I status bit to the INT pin of the
RCS_2488. When PRBS_ERR_EN is set to logic one, an interrupt on the INT is generated
upon assertion of the PRBS_ERR_I register bit. When PRBS_ERR_EN is set low, a change
in the PRBS_ERR_I status does not generate an interrupt.
The PRBS Synchronized Enable bit connects the PRBS_SYNC_I status bit to the INT pin of
the RCS_2488. When PRBS_SYNC_EN is set to logic one, an interrupt on the INT is
generated upon assertion of the PRBS_SYNC_I register bit. When PRBS_SYNC_EN is set
low, a change in the PRBS_SYNC_I status does not generate an interrupt.
The Signal Detect Disable bit controls the operation of the SD input pin. When
SD_DISABLE is set to a logic one the SD input will be ignored and the internal signal will
be forced to the active state and all down stream blocks will operate normally. When
SD_DISABLE is set to logic zero the internal signal follows the state of the SD input pin and
the state of SD_INV bit.
S/UNI-2488 Telecom Standard Product Datasheet
Released
155

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