PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 158

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0013H: Rx2488 Analog CRU Clock Training Configuration and Status
INDATA
INLOCK
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The clock difference detector DATA TO LOCK transition configuration bit determines the
number of times the clock difference detector must pass before the CRU control state
machine transitions from the LOCKED TO REFERENCE state to the DATA IN RANGE
state. When INDATA is a logic zero, the clock difference detector must pass once before the
state transition can occur. When INDATA is a logic one, the clock difference detector must
pass 39 consecutive times before the state transition can occur.
The clock difference detector LOCKING TO DATA transition configuration bit determines
the number of times the clock difference detector must pass before the CRU control state
machine transitions from the DATA IN RANGE state to the LOCKED TO DATA state.
When INLOCK is a logic zero, the clock difference detector must pass once before the state
transition can occur. When INLOCK is a logic one, the clock difference detector must pass
39 consecutive times before the state transition can occur.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
Function
LOS_COUNT[4]
LOS_COUNT[3]
LOS_COUNT[2]
LOS_COUNT[1]
LOS_COUNT[0]
LOSEN
LINE_LOOP_BACK
SDI_INV
INV_DATA
DOOLV
ROOLV
TRAIN
OUTLOCK
OUTDATA
INLOCK
INDATA
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
1
0
0
0
1
0
0
0
X
X
X
1
1
1
1
Released
158