PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 160

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
DOOLV
INV_DATA
SDI_INV
LINE_LOOP_BACK
LOSEN
The recovered data out of lock status indicates that the clock recovery phase locked loop is
unable to recover and lock to the input data stream. DOOLV is logic one if the divided down
recovered clock frequency is not within approximately 488ppm of the REFCLK frequency or
if LOS_I interrupt has been triggered.
The Serial Data Inversion INV_DATA controls the polarity of the received data. When
INV_DATA is set to ‘1’, the polarity of the RXD_P/RXD_N input pins invert. When
INV_DATA is set to ‘0’, the RXD_P/RXD_N inputs operate normally.
The Signal Detect Inversion INV_SD controls the polarity of the SD input pin. When
INV_SD is set to ‘1’ the polarity of the SD input pin is inverted. When INV_SD is set to ‘0’
the polarity of the SD input remains unchanged.
The line loop back bit selects the source of the timing for the parallel data output of the
receive FIFO. When the LINE_LOOP_BACK is set to logic one, the output data of this
FIFO is timed to the clock of the S/UNI-2488 transmitter. Either the S/UNI-2488 or the
upstream device must be in loop-timed mode for the line-loopback mode to work properly.
When reset to logic zero, the receive FIFO output data is timed using either the receive-side-
CRU clock.
For chip-level line loopback, this LINE_LOOP_BACK bit and the SLLE register bit in the
Tx2488 Analog Control/Status register (register 0020H) must be set to logic 1. As well, the
CSU_MODE[7] register bit in the Tx2488 ABC Control register (register 0021H) must be set
to logic 0.
The loss of signal enable bit controls the signal detection logic. The CRU uses the LOS
detector along with the clock difference detector to determine if the CRU is locked to data.
When LOSEN is set to logic one, the incoming signal is monitored for 1/0 transitions as
determined by LOS_COUNT[4:0] register bits. If LOSEN is reset to logic zero, the 1/0
transition detector is disabled. Note: recall that LOS_COUNT is specified as the upper 5 bits
of an 11 bit number and has an accuracy of ±15.
S/UNI-2488 Telecom Standard Product Datasheet
Released
160