PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 167

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Reserved1
PD_MON
ROOL_I
The Reserved1 bit must be set to logic 1 for proper operation.
The Phase Detector Monitor bit indicates the state of the Phase Detector state machine. When
PD_MON is logic 0 the CSU state machine is in the Phase & Frequency Detector state. When
PD_MON is set to logic 1 the CSU state machine is in the Hogge-II Phase Detector state.
When in the Hogge-II Phase Detector state, the CSU has locked to the reference.
The transmit recovered reference out of lock status indicates that the clock synthesis phase
locked loop is unable to lock to the reference clock on REFCLK. At startup, ROOL_I may
remain at logic 1 for several hundred milliseconds while the PLL obtains lock. If WCIMODE
is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0,
then a read of this register automatically clears the bit.
The PD_MON register bit can be used to reveal whether the CSU is locked to the reference.
Note: When ROOL_I is set and indicates that the CSU has lost lock to the reference clock,
then once the reference is restored, the CSU must be reset (using CSU_RESET in register
0x0021) before normal operation can begin.
S/UNI-2488 Telecom Standard Product Datasheet
Released
167

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