PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 169

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
IDDQ_ENABLE
Reserved1:
TX2488_ENABLE
For a loop timed mode of operation, the CSUMODE[7] register bit must be set to logic 0. In
this mode of operation, the transmitter timing is derived from the recovered clock. The
S/UNI-2488 cannot be configured for loop time operation if operating with a mate device
unless both received clocks are frequency locked.
The IDDQ_ENABLE bit activates the IDDQ (Quiescent Current) test mode. When set to
‘1’, all TX2488 Analog Circuits are disabled and the IDDQ of the digital circuits can be
measured. When this bit is set to ‘0’, all TX2488 analog circuits operate normally. This bit is
only used during production testing.
The Reserved1 bit must be set to logic1 for proper operation.C2C_ENABLE
The CML to CMOS Interface Module Enable provides a global power down of the
CML2CMOS-RX2488 Analog Block Circuit. When set to ‘0’, this bit forces the CML to
CMOS Interface Module to a low power state and functionality is disabled. When set to ‘1’,
the CML to CMOS Interface Module operates in the normal mode of operation.
The 2.488GHz Transmitter Enable provides a global power down of the TX2488 Analog
Block Circuit. When set to ‘0’, this bit forces the TX2488 to a low power state and
functionality is disabled. When set to ‘1’, the TX2488 operates in the normal mode of
operation.
Mode Bits
3
2
1:0
Description
Reserved
Selects the type of phase detector used in the PLL after the
frequency lock is achieved.
0 - Phase & Frequency Detector (a.k.a. PFD) (Default)
1 - Hogge-II Phase Detector.
NOTE: PFD is the default mode for start-up. Once the frequency lock
is achieved, switching to Hogge mode will reduce the intrinsic jitter by
about 10%. In Hogge-II mode the resistor value must be 10KW. If
after frequency lock, the PFD mode is continued to be used for
normal operation (10% more jitter), the optimum resistor for PFD is
12.5KW. During start-up either 12.5KW or 10KW can be used with
PFD. (For resistor value selections, see CSU_MODE[6:5])
Reserved
S/UNI-2488 Telecom Standard Product Datasheet
Released
169