PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 170

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RX_REF_ENABLE
CSU_RESET
PISO_RESET
Reserved
The PECL Reference Clock Receiver Enable provides a global power down of the RX2488-
PECL Analog Block Circuitry used for reference clock input. When set to ‘0’, this bit forces
the block to a low power state and functionality is disabled. When set to ‘1’, the block
operates in the normal mode of operation.
The Clock Source Unit Reset provides a complete reset of the CSU2488 Analog Block
Circuit. When set to ‘1’, this bit forces the CSU to a known initial state. While the bit is set to
‘1’, the functionality of the block is disabled. When set to ‘0’, the CSU operates in the normal
mode of operation. This bit is not self-clearing. Therefore a ‘0’ must be written to the bit to
remove the reset condition.
When asserted, CSU_RESET must be set to logic 1 for at least 2ms.
The PISO Reset provides a complete reset of the PISO-2488 Analog Block Circuit. When set
to ‘1’, this bit forces the PISO to a known initial state. While the bit is set to ‘1’, the
functionality of the block is disabled. When set to ‘0’, the PISO operates in the normal mode
of operation. This bit is not self-clearing. Therefore a ‘0’ must written to the bit to remove the
reset condition.
This bit must be set to logic 0 for proper operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
170