PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 172

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0030H: SRLI Clock Configuration
The Clock Configuration Register is provided at SRLI r/w address 0030H.
All Reserved bits must be set to their default values for proper operation.
RCLKEN
DISFRM
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The receive clock enable (RCLKEN) bit controls the gating of the RCLK output clock.
When RCLKEN is set to logic 1, the RCLK output clock operates normally. When RCLKEN
is set to logic 0, the RCLK output clock is held low.
The disable framing (DISFRM) bit disables the framing algorithm and resets the bit
alignment on the RD[15:0] input bus to none. When DISFRM is set to logic 1, the framing
algorithm is disabled and the bit alignment is reset to none. When DISFRM is set to logic 0,
the framing algorithm is enable and the bit alignment is done when out of frame is declared.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Reserved
DISFRM
Reserved
Reserved
Reserved
RCLKEN
Function
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Default
1
0
0
0
0
0
0
0
0
0
Released
172