PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 183
PM5381-BI
Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5381-BI.pdf
(586 pages)
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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
LAISI
LRDII
APSBFI
COAPSI
COSSMI
SBIPEI
The line alarm indication signal interrupt status (LAISI) bit is an event indicator. LAISI is set
to logic 1 to indicate any change in the status of LAISV. The interrupt status bit is
independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-writing
with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears the bit.
The line remote defect indication interrupt status (LRDII) bit is an event indicator. LRDII is
set to logic 1 to indicate any change in the status of LRDIV. The interrupt status bit is
independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-writing
with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears the bit.
The APS byte failure interrupt status (APSBFI) bit is an event indicator. APSBFI is set to
logic 1 to indicate any change in the status of APSBFV. The interrupt status bit is
independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-writing
with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears the bit.
The change of APS bytes interrupt status (COAPSI) bit is an event indicator. COAPSI is set
to logic 1 to indicate new APS bytes. The interrupt status bit is independent of the interrupt
enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The change of SSM message interrupt status (COSSMI) bit is an event indicator. COSSMI is
set to logic 1 to indicate a new SSM message. The interrupt status bit is independent of the
interrupt enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this
bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
The section BIP error interrupt status (SBIPEI) bit is an event indicator. SBIPEI is set to
logic 1 to indicate a section BIP error. The interrupt status bit is independent of the interrupt
enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If
WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
S/UNI-2488 Telecom Standard Product Datasheet
Released
183
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