PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 192

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0080H: TRMP Configuration
All Reserved bits must be set to their default values for proper operation.
A1A2EN
Z0DEF
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The A1A2 framing enable (A1A2EN) bit controls the insertion of the framing bytes in the
data stream. When A1A2EN is set to logic 1, F6h and 28h are inserted in the A1 and A2
bytes according to the priority of Table 4. When A1A2EN is set to logic 0, the framing bytes
are not inserted.
For normal operation, the A1A2EN bits in the TRMP Aux2 Configuration register, the TRMP
Aux3 Configuration register and the TRMP Aux4 Configuration register must be set to the
same value as the A1A2EN bit.
The Z0 definition (Z0DEF) bit defines the Z0 growth bytes. When Z0DEF is set to logic 0,
the Z0 bytes are defined according to BELLCORE. The Z0 bytes are located in STS-1/STM-
0 #2 to #48. Z0DEF must be set to logic 0 for proper operation.
For normal operation, the Z0DEF bits in the TRMP Aux2 Configuration register, the TRMP
Aux3 Configuration register and the TRMP Aux4 Configuration register must be set to the
same value as the Z0DEF bit.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Unused
Unused
LREIBLK
LREIEN
APSEN
Reserved
TLDEN
Reserved
Reserved
TSLDEN
TRACEEN
J0Z0INCEN
Z0DEF
A1A2EN
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
1
1
1
0
0
1
0
0
0
0
1
Released
192