PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 195

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0081H: TRMP Register Insertion
J0REGEN
Z0REGEN
E1REGEN
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The J0 register enable (J0REGEN) bit controls the insertion of section trace in the data
stream. When J0REGEN is set to logic 1, the section trace from the TRMP Transmit J0 and
Z0 register is inserted in the J0 byte of STS-1/STM-0 #1 according to the priority of Table 4.
When J0REGEN is set to logic 0, the section trace from the TRMP Transmit J0 and Z0
register is not inserted.
The Z0 register enable (Z0REGEN) bit controls the insertion of Z0 growth bytes in the data
stream. When Z0REGEN is set to logic 1, the Z0 growth byte from the TRMP Transmit J0
and Z0 register is inserted in the Z0 bytes according to the priority of Table 4. When
Z0REGEN is set to logic 0, the Z0 growth byte from the TRMP Transmit J0 and Z0 register is
not inserted. The Z0DEF bit in the TRMP Configuration register defines the Z0 bytes.
The E1 register enable (E1REGEN) bit controls the insertion of section order wire in the data
stream. When E1REGEN is set to logic 1, the section order wire from the TRMP Transmit
E1 and F1 register is inserted in the E1 byte of STS-1/STM-0 #1 according to the priority of
Table 4. When E1REGEN is set to logic 0, the section order wire from the TRMP Transmit
E1 and F1 register is not inserted.
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UNUSEDV
UNUSEDEN
NATIONALV
NATIONALEN
Unused
E2REGEN
Z2REGEN
Z1REGEN
S1REGEN
D4D12REGEN
K1K2REGEN
D1D3REGEN
F1REGEN
E1REGEN
Z0REGEN
J0REGEN
Function
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Released
195