PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 230

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
RWB
BUSY
The active high read and active low write (RWB) bit selects if the current access to the
internal RAM is an indirect read or an indirect write. Writing to the Indirect Address Register
initiates an access to the internal RAM. When RWB is set to logic 1, an indirect read access
to the RAM is initiated. The data from the addressed location in the internal RAM will be
transferred to the Indirect Data Register. When RWB is set to logic 0, an indirect write access
to the RAM is initiated. The data from the Indirect Data Register will be transferred to the
addressed location in the internal RAM.
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal RAM has been completed. BUSY is set to logic 1 upon writing to the Indirect
Address Register. BUSY is set to logic 0 upon completion of the RAM access. This register
should be polled to determine when new data is available in the Indirect Data Register.
S/UNI-2488 Telecom Standard Product Datasheet
Released
230