PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 237

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0137H: RTTP SECTION Trace Mismatch Interrupt Status
All Reserved bits must be set to their default values for proper operation.
TIMI
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The trace identifier mismatch interrupt status (TIMI) bit is an event indicator. TIMI is set to
logic 1 to indicate any changes in the status of TIMV (match to mismatch, mismatch to
match). This interrupt status bit is independent of the interrupt enable bit. If WCIMODE is
set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then
a read of this register automatically clears the bit.
Type
R
R
R
R
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TIMI
Default
X
X
X
X
X
X
X
X
X
X
X
X
S/UNI-2488 Telecom Standard Product Datasheet
Released
237

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