PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 245

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0139H: TTTP SECTION Indirect Data
DATA[15:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The indirect access data (DATA[15:0]) bits hold the data transfer to or from the internal RAM
during indirect access. When RWB is set to logic 1 (indirect read), the data from the
addressed location in the internal RAM will be transferred to DATA[15:0]. BUSY should be
polled to determine when the new data is available in DATA[15:0]. When RWB is set to
logic 0 (indirect write), the data from DATA[15:0] will be transferred to the addressed
location in the internal RAM. The indirect Data register must contain valid data before the
indirect write is initiated by writing to the Indirect Address Register.
DATA[15:0] has a different meaning depending on which address of the internal RAM is
being accessed.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
245