PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 252

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PM5381-BI

Manufacturer Part Number
PM5381-BI
Description
ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
Manufacturer
PMC-Sierra, Inc.
Datasheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
INVCNT
NDFCNT
The invalid counter (INVCNT) bit selects the behavior of the consecutive INV_POINT event
counter in the pointer interpreter state machine. When INVCNT is set to logic 1, the
consecutive INV_POINT event counter is reset by 3 EQ_NEW_POINT indications. When
INVCNT is set to logic 0, the counter is not reset by 3 EQ_NEW_POINT indications.
INVCNT must be set to logic 1 to enable behaviour compliant to GR-253 CORE.
The new data flag counter (NDFCNT) bit selects the behavior of the consecutive
NDF_ENABLE event counter in the pointer interpreter state machine. When NDFCNT is set
to logic 1, the NDF_ENABLE definition is enabled NDF + ss. When NDFCNT is set to logic
0, the NDF_ENABLE definition is enabled NDF + ss + offset value in the range 0 to 782.
This configuration bit only changes the NDF_ENABLE definition for the consecutive
NDF_ENABLE event counter to count towards LOP-P defect when the pointer is out of
range. This configuration bit does not change the NDF_ENABLE definition for pointer
justification.
S/UNI-2488 Telecom Standard Product Datasheet
Released
252

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