PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 257

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 03H: RHPP Captured and Accepted PSL
The Accepted PSL and ERDI Indirect Register is provided at RHPP r/w address 03H.
APSLV[7:0]
CPSLV[7:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The accepted path signal label value (APSLV[7:0]) bits represent the last accepted path signal
label value. APSLV is updated differently depending on how the ALGO2 bit in RHPP
indirect register 01H is set. When ALGO2 is logic 1, a new PSL is accepted when the same
PSL value is detected in the C2 byte for three or five consecutive frames. (selectable with the
PSL5 register bit). When ALGO2 is logic 0, APSLV is updated every time a new PSL is
received. Note that there is no concept of “accepted” path signal label in Algorithm 1, so this
register should only be used when ALGO2 is logic 1.
The captured path signal label value (CPSLV[7:0]) bits represent the last captured path signal
label value. A new PSL is captured every frame from the C2 byte.
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
CPSLV[7]
CPSLV[6]
CPSLV[5]
CPSLV[4]
CPSLV[3]
CPSLV[2]
CPSLV[1]
CPSLV[0]
APSLV[7]
APSLV[6]
APSLV[5]
APSLV[4]
APSLV[3]
APSLV[2]
APSLV[1]
APSLV[0]
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Released
257