PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 258

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 04H: RHPP Expected PSL and PDI
The Expected PSL and PDI Indirect Register is provided at RHPP r/w indirect address 04H.
EPSL[7:0]
PDI[4:0], PDIRANGE
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The expected path signal label (EPSL[7:0]) bits represent the expected path signal label. The
expected PSL and the expected PDI validate the received or the accepted PSL to declare
PLM-P, UNEQ-P and PDI-P defects according Table 1.
The payload defect indication (PDI[4:0]) bits and the payload defect indication range
(PDIRANGE) bit determine the expected payload defect indication according to Table 2.
When PDIRANGE is set to logic 1, the PDI range is enabled and the expected PDI range is
from E1H to E0H+PDI[4:0]. When PDIRANGE is set to logic 0, the PDI range is disabled
and the expected PDI value is E0H+PDI[4:0]. The expected PSL and the expected PDI
validate the received or the accepted PSL to declare PLM-P, UNEQ-P and PDI-P defects
according Table 1.
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
PDIRANGE
PDI[4]
PDI[3]
PDI[2]
PDI[1]
PDI[0]
EPSL[7]
EPSL[6]
EPSL[5]
EPSL[4]
EPSL[3]
EPSL[2]
EPSL[1]
EPSL[0]
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Released
258