PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 275

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PJEI
PLOPI
PAISI
PLOPCI
The positive pointer justification event interrupt status (PJEI) bit is an event indicator. PJEI
is set to logic 1 to indicate a positive pointer justification event. The interrupt status bit is
independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-writing
with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears the bit.
This bit is only valid for RHPP STS-1/STM0 #1 except in the XCONNECT mode of
operation.
The path loss of pointer interrupt status (PLOPI) bit is an event indicator. PLOPI is set to
logic 1 to indicate any change in the status of PLOPV (entry to the LOP_state or exit from the
LOP_state). The interrupt status bit is independent of the interrupt enable bit. If WCIMODE
is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0,
then a read of this register automatically clears the bit.
This bit is only valid for RHPP STS-1/STM0 #1 except in the XCONNECT mode of
operation.
The path alarm indication signal interrupt status (PAISI) bit is an event indicator. PAISI is set
to logic 1 to indicate any change in the status of PAISV (entry to the AIS_state or exit from
the AIS_state). The interrupt status bit is independent of the interrupt enable bit. If
WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set
to logic 0, then a read of this register automatically clears the bit.
This bit is only valid for RHPP STS-1/STM0 #1 except in the XCONNECT mode of
operation.
The path loss of pointer concatenation interrupt status (PLOPCI) bit is an event indicator.
PLOPCI is set to logic 1 to indicate any change in the status of PLOPCV (entry to the
LOPC_state or exit from the LOPC_state). The interrupt status bit is independent of the
interrupt enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this
bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
This bit is only valid for RHPP STS-1/STM0 #2-48 except in the XCONNECT mode of
operation.
S/UNI-2488 Telecom Standard Product Datasheet
Released
275