PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 278

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PPLMV
PUNEQV
PPDIV
PRDIV
The path payload label mismatch status (PPLMV) bit indicates the current status of the PLM-
P defect.
Algorithm 1: PPLMV is set to logic 1 when the received PSL does not match, according to
Table 1, the expected PSL for 3 or 5 consecutive frames (selectable with the PSL5 register
bit). PPLMV is set to logic 0 when the received PSL matches, according to Table 1, the
expected PSL for 3 or 5 consecutive frames.
Algorithm 2: PPLMV is set to logic 1 when the accepted PSL does not match, according to
Table 1, the expected PSL. PPLMV is set to logic 0 when the accepted PSL matches,
according to Table 1, the expected PSL.
The path unequipped status (PUNEQV) bit indicates the current status of the UNEQ-P defect.
PUNEQV is set to logic 1 when the received PSL indicates unequipped, according to Table 1,
for 3 or 5 consecutive frames (selectable with the PSL5 register bit). A PUNEQV is set to
logic 0 when the received PSL indicates not unequipped, according to Table 1, for 3 or 5
consecutive frames.
The path payload defect indication status (PPDIV) bit indicates the current status of the
PPDI-P defect.
Algorithm 1: PPDIV is set to logic one when the received PSL is a defect, according to Table
1, 3 or 5 consecutive frames (selectable with the PSL5 register bit). PPDIV is set to logic 0
when the received PSL is not a defect, according to Table 1, for 3 or 5 consecutive frames.
Algorithm 2: PPDIV is set to logic 1 when the accepted PSL is a defect according to Table 1.
PPDI is set to logic 0 when the accepted PSL is not a defect according to Table 1.
The path remote defect indication status (PRDIV) bit indicates the current status of the RDI-P
defect. PRDIV is set to logic 1 when bit 5 of the G1 byte is set high for five or ten
consecutive frames (selectable with the PRDI10 register bit). PRDIV is set to logic 0 when
bit 5 of the G1 byte is set low for five or ten consecutive frames.
S/UNI-2488 Telecom Standard Product Datasheet
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