PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 284

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
PPLMI
PUNEQI
PPDII
PRDII
PERDII
The path payload label mismatch interrupt status (PPLMI) bit is an event indicator. PPLMI is
set to logic 1 to indicate any change in the status of PPLMV (match to mismatch or mismatch
to match). The interrupt status bit is independent of the interrupt enable bit. If WCIMODE is
set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then
a read of this register automatically clears the bit.
The path payload unequipped interrupt status (PUNEQI) bit is an event indicator. PUNEQI is
set to logic 1 to indicate any change in the status of PUNEQV (equipped to unequipped or
unequipped to equipped). The interrupt status bit is independent of the interrupt enable bit.
If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is
set to logic 0, then a read of this register automatically clears the bit.
The path payload defect indication interrupt status (PPDII) bit is an event indicator. PPDII is
set to logic 1 to indicate any change in the status of PPDIV (no defect to payload defect or
payload defect to no defect). The interrupt status bit is independent of the interrupt enable
bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE
is set to logic 0, then a read of this register automatically clears the bit.
The path remote defect indication interrupt status (PRDII) bit is an event indicator. PRDII is
set to logic 1 to indicate any change in the status of PRDIV (no defect to RDI defect or RDI
defect to no defect). The interrupt status bit is independent of the interrupt enable bit. If
WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set
to logic 0, then a read of this register automatically clears the bit.
The path enhanced remote defect indication interrupt status (PERDII) bit is an event
indicator. PERDII is set to logic 1 to indicate any change in the status of PERDIV (no defect
to ERDI defect or ERDI defect to no defect). The interrupt status bit is independent of the
interrupt enable bit. If WCIMODE is set to logic 1, only over-writing with a ‘1’ clears this
bit. If WCIMODE is set to logic 0, then a read of this register automatically clears the bit.
S/UNI-2488 Telecom Standard Product Datasheet
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