PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 287

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
IADDR[3:0]
RWB
BUSY
The address location (IADDR[3:0]) bits select which address location is accessed by the
current indirect transfer.
The active high read and active low write (RWB) bit selects if the current access to an
internal register is an indirect read or an indirect write. Writing to the Indirect Address
Register initiates an access to a register. When RWB is set to logic 1, an indirect read access
to a register is initiated. The data from the addressed location as indicated using the IADDR
field will be transferred to the Indirect Data Register. When RWB is set to logic 0, an indirect
write access to a register is initiated. The data from the Indirect Data Register will be
transferred to the addressed register.
The active high busy (BUSY) bit reports if a previously initiated indirect access to an internal
register has been completed. BUSY is set to logic 1 upon writing to the Indirect Address
Register. BUSY is set to logic 0 upon completion of the access. This register should be
polled to determine when new data is available in the Indirect Data Register.
IADDR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
Indirect Register
THPP Control Register
THPP Source and Pointer Control
Reserved
Reserved
THPP B3 Mask and Fixed stuff byte
THPP Transmit C2 and J1
THPP Transmit H4 Mask and G1
THPP Transmit F2 and Z3
THPP Transmit Z4 and Z5
Unused
S/UNI-2488 Telecom Standard Product Datasheet
Released
287