PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 297

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Indirect Register 07H: THPP Transmit F2 and Z3 POH (TF2Z3POH)
Z3[7:0]
F2[7:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Z3[7:0] bits are inserted in the Z3 byte position when the SRCZ3 bit of the THPP Source
and Pointer Control Register is logic 0 and input TPOHEN is low during the path Z3 growth
bit positions in the path overhead input stream, TPOH. Z3[7:0] is inserted into the Z3 position
of the POH when register insertion is enabled. See Table 6 Path Overhead Byte Source
Priority for details.
This field is only valid for THPP STS-1/STM0 #1.
The F2[7:0] bits are inserted in the F2 byte position when the SRCF2 bit of the THPP Source
and Pointer Control Register is logic 0 and input TPOHEN is low during the path User
Channel bit positions in the path overhead input stream, TPOH. F2[7:0] is inserted into the
F2 position of the POH when register insertion is enabled. See Table 6 Path Overhead Byte
Source Priority for details.
This field is only valid for THPP STS-1/STM0 #1.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
F2[7]
F2[6]
F2[5]
F2[4]
F2[3]
F2[2]
F2[1]
F2[0]
Z3[7]
Z3[6]
Z3[5]
Z3[4]
Z3[3]
Z3[2]
Z3[1]
Z3[0]
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
297