PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 303

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
STS3C[3]
STS3C[4]
SLAVE
STS12C
The STS-3c (VC-4) payload configuration (STS3C[3]) bit selects the payload configuration.
When STS3C[3] is set to logic 1, the STS-1/STM-0 paths #3, #7 and #11 are part of a STS-3c
(VC-4) payload. When STS3C[3] is set to logic 0, the paths are STS-1 (VC-3) payloads. The
STS12C register bit has precedence over the STS3C[3] register bit.
The STS-3c (VC-4) payload configuration (STS3C[4]) bit selects the payload configuration.
When STS3C[4] is set to logic 1, the STS-1/STM-0 paths #4, #8 and #12 are part of a STS-3c
(VC-4) payload. When STS3C[4] is set to logic 0, the paths are STS-1 (VC-3) payloads. The
STS12C register bit has precedence over the STS3C[4] register bit.
The STS-12c/VC-4-4c slave concatenation (SLAVE) signal enables the slave processing of
an STS-12c/VC-4-4c payload. When SLAVE is logic one, the SVCA processes a slave
STS-12c/VC-4-4c payload. When SLAVE is logic zero, the SVCA processes a master
STS-12c/VC-4-4c payload. One master SVCA and three slave SVCA can be used to process
an STS-48c/VC-4-16c payload. When SLAVE is logic one, the PTRJE output is simply the
SLPTRJE input. When STS12CSL is logic zero, the PTRJE output is derived from the
pointer generator state machine and the SLPTRJE input is ignored.
The SLAVE register bit is OR’ed with the SLAVE input. The SLAVE register bit has
precedence over the STS3C[1:4] register bit.
The STS-12c (VC-4-4c) payload configuration (STS12C) bit selects the payload
configuration. When STS12C is set to logic 1, the STS-1/STM-0 paths #1 to #12 are part of
an STS-12c (VC-4-4c) payload. When STS12C is set to logic 0, the STS-1/STM-0 paths are
defined with the STS3C[1:4] register bit. The STS12C register bit is OR’ed with the STS12C
input. The STS12C register bit has precedence over the STS3C[1:4] register bit.
S/UNI-2488 Telecom Standard Product Datasheet
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