PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 306

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0605H, 0625H, 0645H, 0665H: SVCA FIFO Overflow Interrupt Status
In the XCONNECT mode of operation of the S/UNI-2488, the FOVRI[12:1] register bits are
defined as follows:
FOVRI[12:1]
FOVRI[1]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The FIFO overflow event interrupt status (FOVRI[12:1]) bits are event indicators for STS-
1/STM-0 paths #1 to #12. FOVRI[12:1] are set to logic 1 to indicate a FIFO overflow event.
These interrupt status bits are independent of the interrupt enable bits. If WCIMODE is set to
logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read
of this register automatically clears this bit.
In the normal mode of operation of the S/UNI-2488 only the first register address (0605H) is
used. The FOVRI[12:2] register bits are unused in normal mode and the FOVRI[1] register
bit is defined as follows:
The FIFO overflow event interrupt status (FOVRI[1]) bit indicates a FIFO overflow in the
SVCA. FOVRI[1] is set to logic 1 to indicate a FIFO overflow event. This interrupt status
bit is independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-
writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears this bit.
Type
R
R
R
R
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
FOVRI[12]
FOVRI[11]
FOVRI[10]
FOVRI[9]
FOVRI[8]
FOVRI[7]
FOVRI[6]
FOVRI[5]
FOVRI[4]
FOVRI[3]
FOVRI[2]
FOVRI[1]
Default
0
0
0
0
0
0
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
306