PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 307

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0606H, 0626H, 0646H, 0666H: SVCA FIFO Underflow Interrupt Status
In the XCONNECT mode of operation of the S/UNI-2488, the FUDRI[12:1] register bits are
defined as follows:
FUDRI[12:1]
FUDRI[1]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The FIFO underflow event interrupt status (FUDR[12:1]) bits are event indicators for STS-
1/STM-0 paths #1 to #12. FUDRI[12:1] are set to logic 1 to indicate a FIFO underflow
event. These interrupt status bits are independent of the interrupt enable bits. If WCIMODE
is set to logic 1, only over-writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0,
then a read of this register automatically clears this bit.
In the normal mode of operation of the S/UNI-2488 only the first register address (0606H) is
used. The FUDRI[12:2] register bits are unused in normal mode and the FUDRI[1] register
bit is defined as follows:
The FIFO underflow event interrupt status (FUDRI[1]) bit indicates a FIFO underflow in the
SVCA. FUDRI[1] is set to logic 1 to indicate a FIFO underflow event. This interrupt status
bit is independent of the interrupt enable bit. If WCIMODE is set to logic 1, only over-
writing with a ‘1’ clears this bit. If WCIMODE is set to logic 0, then a read of this register
automatically clears this bit.
Type
R
R
R
R
R
R
R
R
R
R
R
R
Function
Unused
Unused
Unused
Unused
FUDRI[12]
FUDRI[11]
FUDRI[10]
FUDRI[9]
FUDRI[8]
FUDRI[7]
FUDRI[6]
FUDRI[5]
FUDRI[4]
FUDRI[3]
FUDRI[2]
FUDRI[1]
Default
0
0
0
0
0
0
0
0
0
0
0
0
S/UNI-2488 Telecom Standard Product Datasheet
Released
307