PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 330

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
NOSYNC
PER5
ZEROEN
SYNC_CRLF
The synchronization disable (NOSYNC) bit disables the synchronization of the tail trace
message in algorithm 1 and algorithm 2. When NOSYNC is set to logic 1, no
synchronization is done on the tail trace message. The bytes of the tail trace message are
written in the captured page as in a circular buffer. When NOSYNC is set to logic 0,
synchronization is done on the tail trace message. When LENGTH16 is set to logic 1, the tail
trace message is synchronized on the MSB of the tail trace message. The byte with its MSB
set high is placed in the first byte location of the captured page. When LENGTH16 is set to
logic 0, the tail trace message is synchronize on the CR/LF (CR = 0Dh, LF = 0Ah) characters
of the tail trace message. The byte following the CR/LF bytes is placed in the first byte
location of the captured page.
The message persistency (PER5) bit selects the number of multi-frames a tail trace message
must receive in order to be declared persistent in algorithm 2. When PER5 is set to logic 1,
the same tail trace message must be receive for 5 consecutive multi-frames to be declared
persistent. When PER5 is set to logic 0, the same tail trace message must be received for 3
consecutive multi-frames to be declared persistent.
The all zero message enable (ZEROEN) bit selects if the all zero message is validated or not
against the expected message in algorithm 1 and algorithm 2. When ZEROEN is set to logic
1, an all zero captured message in algorithm 1 and an all zero accepted message in algorithm
2 are validated against the expected message. A match is declared when both the
captured/accepted message and the expected message are all zero. When ZEROEN is set to
logic 0, an all zero captured message in algorithm 1 and an all zero accepted message in
algorithm 2 are not validated against the expected message but are considered to match. A
match is declared when the captured/accepted message is all zero regardless of the expected
message.
The synchronization on CR/LF characters (SYNC_CRLF) bit selects if the current algorithm
(except algo3) synchronizes on the CR/LF ASCII characters or on the byte with its MSB set
high. When SYNC_CRLF is set to logic 1, the current algorithm synchronizes when it
receives the ASCII character “CR” (carriage return) followed by “LF” (line feed) and the
current active byte becomes the last byte of the message. When SYNC_CRLF is set to 0, the
current algorithm synchronizes when receiving a byte with its MSB set to logic 1. The
current active byte then becomes the first byte of the message.
S/UNI-2488 Telecom Standard Product Datasheet
Released
330