PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 35

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
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The Receive ATM Processor
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The Receive POS Processor
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Extracts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the
receive stream. Detects an unstable message or mismatch message with an expected message.
Provides access to the captured, accepted and expected message via the microprocessor port.
Inserts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the
transmit stream.
Detects received path BIP-8 and counts received path BIP-8 errors for performance
monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis.
Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
Counts received path remote error indications (REI’s) for performance monitoring purposes.
Optionally inserts the path REI count into the path status byte (G1) based on bit or block
BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block basis
independent of the accumulation of BIP-8 errors.
Provides automatic transmit path RDI and path Enhanced RDI insertion following detection
of various received alarms (LAIS, LOP, LOPCON, PAIS, PAISCON, PTIM, PTIU, PLM,
PLU, UNEQ, PDI).
Extracts ATM cells from the received STS-48c/STM-16c channel payloads using ATM cell
delineation.
Provides ATM cell payload de-scrambling.
Performs header check sequence (HCS) error detection, and idle/unassigned cell filtering.
Detects out of cell delineation (OCD) and loss of cell delineation (LCD) alarms.
Counts the number of received cells, idle cells, erroneous cells and dropped cells.
Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up
to 104 MHz) with parity support to read extracted cells from an internal 48 cell FIFO buffer.
Supports packet based link layer protocols using byte synchronous HDLC framing.
Performs self-synchronous POS data de-scrambling on the received STS-48c/STM16c-16c
payloads using the x
Performs flag sequence detection and terminates the received POS frames.
Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.
Performs control escape de-stuffing or byte de-stuffing of the POS stream.
Detects packet abort sequence.
Checks for minimum and maximum packet lengths. Optionally deletes short packets and
marks those exceeding the maximum length as erroneous.
Permits FCS stripping on the POS-PHY output data stream.
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+1 polynomial.
S/UNI-2488 Telecom Standard Product Datasheet
Released
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